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公开(公告)号:US20190042357A1
公开(公告)日:2019-02-07
申请号:US16141862
申请日:2018-09-25
Applicant: INTEL CORPORATION
Inventor: Wei WU
Abstract: Provided are an apparatus, memory device, and method to determine error location polynomial coefficients to provide to bit correction logic instances to decode bits of a codeword. A memory controller for a memory includes coefficient generating logic to receive as input a plurality of syndrome values to generate a plurality of coefficients for an error locator polynomial. A plurality of instances of bit correction logic, one instance for each bit of bits to correct in a codeword for a block in the memory array to decode. Each instance of bit correction logic is to receive as input the coefficients for the error locator polynomial and elements for the bit to correct from a decoder alphabet to determine whether to correct the bit and output as a decoded bit the bit or a corrected bit to include in a decoded codeword.
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公开(公告)号:US20180082176A1
公开(公告)日:2018-03-22
申请号:US15273505
申请日:2016-09-22
Applicant: INTEL CORPORATION
Inventor: Wei WU , Charles AUGUSTINE , Somnath PAUL
Abstract: Provided are a neuromorphic computing device, memory device, system, and method to maintain a spike history for neurons in a spiking neural network. A neural network spike history is generated in a memory device having an array of rows and columns of memory cells. There is one row of the rows for each of a plurality of neurons and columns for each of a plurality of time slots. Indication is made in a current column in the row of the memory cells for a firing neuron that a spike was fired. Indication is made in the current column in rows of memory cells of idle neurons that did not fire that a spike was not fired. Information in the array is used to determine a timing difference between a connected neuron and the firing neuron and to adjust a weight of the connecting synapse.
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