公开(公告)号：US20220114270A1

公开(公告)日：2022-04-14

申请号：US17560193

申请日：2021-12-22

Applicant: Intel Corporation

Inventor： Ren WANG ,  Sameh GOBRIEL ,  Somnath PAUL ,  Yipeng WANG ,  Priya AUTEE ,  Abhirupa LAYEK ,  Shaman NARAYANA ,  Edwin VERPLANKE ,  Mrittika GANGULI ,  Jr-Shian TSAI ,  Anton SOROKIN ,  Suvadeep BANERJEE ,  Abhijit DAVARE ,  Desmond KIRKPATRICK

IPC: G06F21/62

Abstract: Examples described herein relate to offload circuitry comprising one or more compute engines that are configurable to perform a workload offloaded from a process executed by a processor based on a descriptor particular to the workload. In some examples, the offload circuitry is configurable to perform the workload, among multiple different workloads. In some examples, the multiple different workloads include one or more of: data transformation (DT) for data format conversion, Locality Sensitive Hashing (LSH) for neural network (NN), similarity search, sparse general matrix-matrix multiplication (SpGEMM) acceleration of hash based sparse matrix multiplication, data encode, data decode, or embedding lookup.

公开(公告)号：US20200258890A1

公开(公告)日：2020-08-13

申请号：US16859600

申请日：2020-04-27

Applicant: Intel Corporation

Inventor： Charles AUGUSTINE ,  Somnath PAUL ,  Muhammad M. KHELLAH ,  Chen KOREN

IPC: H01L27/11 ,  G11C11/412 ,  G11C11/419 ,  G11C11/418

Abstract: An ultra-deep compute Static Random Access Memory (SRAM) with high compute throughput and multi-directional data transfer capability is provided. Compute units are placed in both horizontal and vertical directions to achieve a symmetric layout while enabling communication between the compute units. An SRAM array supports simultaneous read and write to the left and right section of the same SRAM subarray by duplicating pre-decoding logic inside the SRAM array. This allows applications with non-overlapping read and write address spaces to have twice the bandwidth as compared to a baseline SRAM array.

公开(公告)号：US20180082176A1

公开(公告)日：2018-03-22

申请号：US15273505

申请日：2016-09-22

Applicant: INTEL CORPORATION

Inventor： Wei WU ,  Charles AUGUSTINE ,  Somnath PAUL

IPC: G06N3/063 ,  G06N3/04

CPC classification number: G06N3/063 ,  G06N3/049 ,  G06N3/088

Abstract: Provided are a neuromorphic computing device, memory device, system, and method to maintain a spike history for neurons in a spiking neural network. A neural network spike history is generated in a memory device having an array of rows and columns of memory cells. There is one row of the rows for each of a plurality of neurons and columns for each of a plurality of time slots. Indication is made in a current column in the row of the memory cells for a firing neuron that a spike was fired. Indication is made in the current column in rows of memory cells of idle neurons that did not fire that a spike was not fired. Information in the array is used to determine a timing difference between a connected neuron and the firing neuron and to adjust a weight of the connecting synapse.

公开(公告)号：US20200183922A1

公开(公告)日：2020-06-11

申请号：US16795516

申请日：2020-02-19

Applicant: Intel Corporation

Inventor： Wootaek LIM ,  Minchang CHO ,  Somnath PAUL ,  Charles AUGUSTINE ,  Suyoung BANG ,  Turbo MAJUMDER ,  Muhammad M. KHELLAH

IPC: G06F16/2453 ,  G06F7/08 ,  G06F7/20 ,  G11C15/04

Abstract: An apparatus is described. The apparatus includes a nearest neighbor search circuit to perform a search according to a first stage search and a second stage search. The nearest neighbor search circuit includes a first stage circuit and a second stage circuit. The first stage search circuit includes a hash logic circuit and a content addressable memory. The hash logic circuit is to generate a hash word from a input query vector. The hash word has B bands. The content addressable memory is to store hashes of a random access memory's data items. The hashes each have B bands. The content addressable memory is to compare the hashes against the hash word on a sequential band-by-band basis. The second stage circuit char the random access memory and a compare and sort circuit. The compare and sort circuit is to receive the input query vector. The random access memory has crosswise bit lines coupled to the compare and sort circuit. The compare and sort circuit is to identify k nearest ones of the data items whose hashes were selected by the content addressable memory.

公开(公告)号：US20190043583A1

公开(公告)日：2019-02-07

申请号：US16110990

申请日：2018-08-23

Applicant: INTEL CORPORATION

Inventor： Turbo MAJUMDER ,  Somnath PAUL ,  Charles AUGUSTINE ,  Muhammad M. KHELLAH

IPC: G11C15/04 ,  G11C8/10 ,  G06F17/30 ,  G06T1/60

Abstract: Provided are an apparatus, video processing unit, and method for clustering events in a content addressable memory. An event is received including at least one parameter value and a timestamp. A determination is made as to whether there is a valid entry in the memory having at least one parameter value within a predefined range of values of the at least one parameter value in the event. In response to a determination that there is the valid entry, writing the at least one parameter value and the timestamp in the event to the valid entry.