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    SHARED PARITY CHECK FOR CORRECTING MEMORY ERRORS
    1.
    发明申请
    SHARED PARITY CHECK FOR CORRECTING MEMORY ERRORS 审中-公开

    公开(公告)号：US20190042358A1

    公开(公告)日：2019-02-07

    申请号：US15890204

    申请日：2018-02-06

    Applicant: Intel Corporation

    Inventor： Kjersten E. CRISS ,  Wei WU

    IPC: G06F11/10 ,  G06F3/06 ,  G11C29/52

    Abstract: Examples include techniques for implementing read and write operations between a memory controller and a memory device. In an embodiment, the memory controller is configured to receive data bits to write to the memory device, to determine, using a memory controller ECC component and the data bits, a plurality of memory controller ECC check bits and one or more parity bits, to append the memory controller ECC check bits and the one or more parity bits to the data bits, and to send the data bits, the memory controller ECC check bits, and the one or more parity bits to the memory device during a write operation. In an embodiment, the memory controller is configured to receive the data bits and the memory controller ECC check bits from the memory device, to check the data bits against the memory controller ECC check bits and correct errors detected, and to return the data bits during a read operation.

    STACKED MEMORY CHIP DEVICE WITH ENHANCED DATA PROTECTION CAPABILITY
    3.
    发明申请
    STACKED MEMORY CHIP DEVICE WITH ENHANCED DATA PROTECTION CAPABILITY 审中-公开

    公开(公告)号：US20190004909A1

    公开(公告)日：2019-01-03

    申请号：US15640182

    申请日：2017-06-30

    Applicant: Intel Corporation

    Inventor： Hussein ALAMEER ,  Uksong KANG ,  Kjersten E. CRISS ,  Rajat AGARWAL ,  Wei WU ,  John B. HALBERT

    IPC: G06F11/16 ,  H01L25/065 ,  G11C5/02 ,  G11C7/24

    Abstract: A stacked memory chip device is described. The stacked memory chip device includes a plurality of stacked memory chips. The stacked memory chip device includes read/write logic circuitry to service read/write requests for cache lines kept within the plurality of stacked memory chips. The stacked memory chip device includes data protection circuitry to store information to protect substantive data of cache lines in the plurality of stacked memory chips, where, the information is kept in more than one of the plurality of stacked memory chips, and where, any subset of the information that protects respective substantive information of a particular one of the cache lines is not stored in a same memory chip with the respective substantive information.

    SPARSE COLUMN-AWARE ENCODINGS FOR NUMERIC DATA TYPES
    8.
    发明申请
    SPARSE COLUMN-AWARE ENCODINGS FOR NUMERIC DATA TYPES 有权

    公开(公告)号：US20210294799A1

    公开(公告)日：2021-09-23

    申请号：US17341963

    申请日：2021-06-08

    Applicant: Intel Corporation

    Inventor： Wei WU ,  Sourabh DONGAONKAR ,  Jawad B. KHAN

    IPC: G06F16/2458 ,  G06F16/248 ,  G06F16/22 ,  G06N3/04

    Abstract: Methods and apparatus for sparse column-aware encodings for numeric data types, including integer data and floating-point data (float, double, etc.). The encoding schemes are tailored to take advantage of column addressable memories such as stochastic associative memories (SAM) to enable Stochastic Associative Search (SAS), which is a highly efficient and fast way of searching through a very large database of records (order of Billions) and finding similar records to a given query record (search key). Techniques are also disclosed for performing range searches for both integer and floating-point data types. The integer or float data is converted to Hexadecimal form and encoded using an m-of-n constant weight encoding. Only the columns with set bits in search keys need to be read, which significantly reduces the number of reads required for searches.

    DYNAMIC RELIABILITY LEVELS FOR STORAGE DEVICES
    9.
    发明申请
    DYNAMIC RELIABILITY LEVELS FOR STORAGE DEVICES 审中-公开

    公开(公告)号：US20190044536A1

    公开(公告)日：2019-02-07

    申请号：US16022631

    申请日：2018-06-28

    Applicant: Intel Corporation

    Inventor： Jawad B. KHAN ,  Sanjeev N. TRIKA ,  Omesh Tickoo ,  Wei WU

    IPC: H03M13/05 ,  G06F11/10 ,  H03M13/00

    CPC classification number: H03M13/05 ,  G06F11/1044 ,  G06F11/1048 ,  H03M13/611

    Abstract: To address the storage needs of applications that work with noisy data (e.g. image, sound, video data), where errors can be tolerated to a certain extent and performance is more critical than data fidelity, dynamic reliability levels enable storage devices capable of storing and retrieving data with varying degrees of data fidelity to dynamically change the degree of data fidelity in response to an application's request specifying reliability level. By allowing the application to specify the reliability level at which its data is stored and retrieved, dynamic reliability levels can increase read/write performance without sacrificing application accuracy. The application can specify reliability levels for different types or units of data, such as different reliability levels for metadata as opposed to data and so forth.

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