公开(公告)号：US20130119512A1

公开(公告)日：2013-05-16

申请号：US13665524

申请日：2012-10-31

Applicant: Intermolecular, Inc. ,  Elpida Memory, Inc

Inventor： Sandra G. Malhotra ,  Hanhong Chen ,  Wim Y. Deweerd ,  Hiroyuki Ode

IPC: H01L29/92

CPC classification number: H01L28/40 ,  H01L21/02186 ,  H01L21/02194 ,  H01L21/0228 ,  H01L21/02304 ,  H01L21/02356 ,  H01L27/10852 ,  H01L28/75

Abstract: A method for forming a DRAM MIM capacitor stack having low leakage current involves the use of a first electrode that serves as a template for promoting the high k phase of a subsequently deposited dielectric layer. The high k dielectric layer comprises a doped material that can be crystallized after a subsequent annealing treatment. A metal oxide second electrode layer is formed above the dielectric layer. The metal oxide second electrode layer has a crystal structure that is compatible with the crystal structure of the dielectric layer. Optionally, a second electrode bulk layer is formed above the metal oxide second electrode layer.

Abstract translation: 用于形成具有低泄漏电流的DRAM MIM电容器堆叠的方法涉及使用用作促进随后沉积的介电层的高k相的模板的第一电极。 高k电介质层包括可在随后的退火处理后结晶的掺杂材料。 金属氧化物第二电极层形成在电介质层的上方。 金属氧化物第二电极层具有与电介质层的晶体结构相容的晶体结构。 可选地，在金属氧化物第二电极层上形成第二电极体层。