公开(公告)号：US10740248B2

公开(公告)日：2020-08-11

申请号：US16218903

申请日：2018-12-13

Applicant: International Business Machines Corporation

Inventor： David Campbell ,  Dwain A. Hicks ,  Christian Jacobi

IPC: G06F12/10 ,  G06F12/1036 ,  G06F12/1018 ,  G06F12/0862 ,  G06F9/38 ,  G06F12/123

Abstract: A method or system of translating a virtualized address to a real address is disclosed that includes receiving a virtualized address for translation; generating a predicted intermediate address translation using a portion of the bit field of the virtualized address; determining a predicted real address using the predicted intermediate address or portion thereof; performing a translation of the virtualized address to an actual intermediate address; determining whether the predicted intermediate address is the same as the actual intermediate address; and in response to the predicted intermediate address being the same as the actual intermediate address, providing the predicted real address as the real address.

公开(公告)号：US20200151097A1

公开(公告)日：2020-05-14

申请号：US16745411

申请日：2020-01-17

Applicant: International Business Machines Corporation

Inventor： Christian Zoellin ,  Christian Jacobi ,  Chung-Lung K. Shum ,  Martin Recktenwald ,  Anthony Saporito ,  Aaron Tsai

IPC: G06F12/0817 ,  G06F12/0831

Abstract: A method and a system detects a cache line as a potential or confirmed hot cache line based on receiving an intervention of a processor associated with a fetch of the cache line. The method and system include suppressing an action of operations associated with the hot cache line. A related method and system detect an intervention and, in response, communicates an intervention notification to another processor. An alternative method and system detect a hot data object associated with an intervention event of an application. The method and system can suppress actions of operations associated with the hot data object. An alternative method and system can detect and communicate an intervention associated with a data object.

公开(公告)号：US10649778B1

公开(公告)日：2020-05-12

申请号：US16208780

申请日：2018-12-04

Applicant: International Business Machines Corporation

Inventor： David Campbell ,  Dwain A. Hicks ,  Christian Jacobi ,  Kerey M. Tassin

IPC: G06F12/00 ,  G06F9/38 ,  G06F9/455 ,  G06F12/14 ,  G06F12/1009 ,  G06F9/46 ,  G06F12/02 ,  G06F12/10

Abstract: A method of optimized congruence class matching for concurrent memory translation requests to avoid memory access conflicts with respect to a virtual memory managed by a processor is provided. The method includes initiating a first table walk by a first memory access of the concurrent memory translation requests and pending a subsequent table walk initiated by a subsequent memory access of the concurrent memory translation requests. Then, the method determines whether the subsequent table walk will cause a memory access conflict with the first table walk based on the optimized congruence class matching. The subsequent memory access is rejected when the subsequent table walk will cause the memory access conflict with the first table walk.

公开(公告)号：US20200142706A1

公开(公告)日：2020-05-07

申请号：US16182017

申请日：2018-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce C. Giamei ,  Martin Recktenwald ,  Donald W. Schmidt ,  Timothy Slegel ,  Aditya N. Puranik ,  Mark S. Farrell ,  Christian Jacobi ,  Jonathan D. Bradbury ,  Christian Zoellin

IPC: G06F9/38 ,  G06F9/30

Abstract: Saving and restoring machine state between multiple executions of an instruction. A determination is made that processing of an operation of an instruction executing on a processor has been interrupted prior to completion. Based on determining that the processing of the operation has been interrupted, current metadata of the processor is extracted. The metadata is stored in a location associated with the instruction and used to re-execute the instruction to resume forward processing of the instruction from where it was interrupted.

公开(公告)号：US20200142696A1

公开(公告)日：2020-05-07

申请号：US16181923

申请日：2018-11-06

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Bruce C. Giamei ,  Martin Recktenwald ,  Donald W. Schmidt ,  Timothy Slegel ,  Aditya N. Puranik ,  Mark S. Farrell ,  Christian Jacobi ,  Jonathan D. Bradbury ,  Christian Zoellin

IPC: G06F9/30

Abstract: A Sort Lists instruction is provided to perform a sort and/or a merge operation. The instruction is an architected machine instruction of an instruction set architecture and is executed by a general-purpose processor of the computing environment. The executing includes sorting a plurality of input lists to obtain one or more sorted output lists, which are output.

公开(公告)号：US10592142B2

公开(公告)日：2020-03-17

申请号：US15281192

申请日：2016-09-30

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： Michael K. Gschwind ,  Christian Jacobi ,  Younes Manton ,  Anthony Saporito ,  Timothy J. Slegel

IPC: G06F12/00 ,  G06F3/06 ,  G06F12/0877 ,  G06F12/0897 ,  G06F12/1027

Abstract: Transient mode for an application is toggled. Transient mode for an application executing in the computing environment is activated. Based on activating transient mode for the application, a plurality of memory accesses are processed as transient accesses. Based on processing the plurality of memory accesses, transient mode for the application is deactivated.

公开(公告)号：US20200073632A1

公开(公告)日：2020-03-05

申请号：US16118560

申请日：2018-08-31

Applicant: International Business Machines Corporation

Inventor： Christian Jacobi ,  Aditya Puranik ,  Martin Recktenwald ,  Christian Zoellin

IPC: G06F7/16 ,  G06F7/02 ,  G06F9/50

Abstract: A computer processor includes a memory unit that stores key values to be loaded into a partial tournament sort, and a processor cache that obtains tree data from the memory unit indicating the key values. A hardware merge sort accelerator generates a tournament tree based on the key values, and performs a partial tournament sort to store a first portion of tournament results in the processor cache while excluding a second portion of the tournament results from the processor cache.

公开(公告)号：US20190303157A1

公开(公告)日：2019-10-03

申请号：US16444694

申请日：2019-06-18

Applicant: International Business Machines Corporation

Inventor： Michael K. Gschwind ,  Christian Jacobi ,  Anthony Saporito ,  Chung-Lung K. Shum

IPC: G06F9/38 ,  G06F12/0862 ,  G06F9/30 ,  G06F12/0875

Abstract: A method, system, and computer program product are provided for prioritizing prefetch instructions. The method includes a processor issuing a prefetch instruction and fetching elements from a cache that can include a memory or a higher level cache. The processor stores the elements in temporary storage and monitors for accesses by an instruction. The processor stores a record representing the prefetch instruction. The processor updates the record with an indicator and issues a new prefetch instruction by comparing the new prefetch instruction to the record, based on the new prefetch instruction matching the prefetch instruction, assigning the indicator to the new prefetch instruction as a priority value, based on the new prefetch instruction not matching the prefetch instruction, assigning a default value to the new prefetch instruction as the priority value, and determining whether to execute the new prefetch instruction, based on the priority value of the new prefetch instruction.

公开(公告)号：US10430195B2

公开(公告)日：2019-10-01

申请号：US15193304

申请日：2016-06-27

Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION

Inventor： James J. Bonanno ,  Michael J. Cadigan, Jr. ,  Adam B. Collura ,  Christian Jacobi ,  Daniel Lipetz ,  Anthony Saporito

IPC: G06F9/38 ,  G06F9/30

Abstract: A computer-implemented method for predicting a taken branch that ends an instruction stream in a pipelined high frequency microprocessor includes receiving, by a processor, a first instruction within a first instruction stream, the first instruction including a first instruction address. The computer-implemented method further includes searching, by the processor, a stream-based index accelerator predictor one time for the stream; determining, by the processor, a prediction for a branch ending the branch stream; influencing, by the processor, a metadata prediction engine based on the prediction; and updating, by the processor, a stream-based index accelerator predictor with information indicative of the prediction.

公开(公告)号：US10430188B2

公开(公告)日：2019-10-01

申请号：US14143325

申请日：2013-12-30

Applicant: International Business Machines Corporation

Inventor： Christian Jacobi ,  Chung-Lung Kevin Shum ,  Timothy J Siegel ,  Gustav E Sittmann, III

IPC: G06F9/34 ,  G06F12/123 ,  G06F9/30 ,  G06F12/0862 ,  G06F9/38 ,  G06F12/0815 ,  G06F12/126

Abstract: Executing a Next Instruction Access Intent instruction by a computer. The processor obtains an access intent instruction indicating an access intent. The access intent is associated with an operand of a next sequential instruction. The access intent indicates usage of the operand by one or more instructions subsequent to the next sequential instruction. The computer executes the access intent instruction. The computer obtains the next sequential instruction. The computer executes the next sequential instruction, whose execution comprises, based on the access intent, adjusting one or more cache behaviors for the operand of the next sequential instruction.