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公开(公告)号：US20180101358A1
公开(公告)日：2018-04-12
申请号：US15840033
申请日：2017-12-13
CPC分类号： G06F7/485 , G06F7/49915 , G06F7/49947
摘要： Arithmetic logic circuitry is provided for performing a floating point arithmetic add/subtract operation on first and second floating point numbers. The method includes: generating a guard digit for the first or second number by transforming the first and second numbers by a compressing function; determining a result depending on the arithmetic operation, a sum of the transformed floating point numbers, and first and second differences of the transformed floating point numbers, and determining a corresponding result plus one by additionally adding a value of one to the result; generating injection values for rounding the final result; generating injection carry values based on the transformed first and second numbers and the injection values; and selecting the final result from the result, the result plus one, and a least significant digit, based on the injection carry values and the end around carry signals.
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公开(公告)号：US09870200B2
公开(公告)日：2018-01-16
申请号：US15354151
申请日：2016-11-17
CPC分类号： G06F7/485 , G06F7/49915 , G06F7/49947
摘要： Arithmetic logic circuitry is provided for performing a floating point arithmetic add/subtract operation on first and second floating point numbers. The method includes: generating a guard digit for the first or second number by transforming the first and second numbers by a compressing function; determining a result depending on the arithmetic operation, a sum of the transformed floating point numbers, and first and second differences of the transformed floating point numbers, and determining a corresponding result plus one by additionally adding a value of one to the result; generating injection values for rounding the final result; generating injection carry values based on the transformed first and second numbers and the injection values; and selecting the final result from the result, the result plus one, and a least significant digit, based on the injection carry values and the end around carry signals.
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公开(公告)号：US20170220319A1
公开(公告)日：2017-08-03
申请号：US15197290
申请日：2016-06-29
CPC分类号： G06F7/4876 , G06F5/01 , G06F5/012 , G06F7/483 , G06F7/485 , G06F7/5443 , G06F2207/483
摘要： A binary fused multiply-add floating-point unit configured to operate on an addend, a multiplier, and a multiplicand. The unit is configured to receive as the addend an unrounded result of a prior operation executed in the unit via an early result feedback path; to perform an alignment shift of the unrounded addend on an unrounded exponent and an unrounded mantissa; as well as perform a rounding correction for the addend in parallel to the actual alignment shift, responsive to a rounding-up signal.
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公开(公告)号：US09348796B2
公开(公告)日：2016-05-24
申请号：US14031854
申请日：2013-09-19
CPC分类号： G06F17/10 , G06F7/535 , G06F7/5375
摘要： An arithmetic operation in a data processing unit, preferably by iterative digit accumulations, is proposed. An approximate result of the arithmetic operation is computed iteratively. Concurrently at least two supplementary values of the approximate result of the arithmetic operation are computed, and the final result selected from one of the values of the approximate result and the at least two supplementary values of the arithmetic operation depending on the results of the last iteration step.
摘要翻译： 提出了数据处理单元中的优选地通过迭代数字积累的算术运算。 迭代地计算算术运算的近似结果。 同时计算算术运算的近似结果的至少两个补充值，并且根据最后一次迭代的结果从算术运算的近似结果和至少两个补充值中的一个值中选出最终结果 步。
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