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公开(公告)号：US6026471A
公开(公告)日：2000-02-15
申请号：US751468
申请日：1996-11-19
申请人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Wilbur David Pricer , Sebastian Theodore Ventrone
发明人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Wilbur David Pricer , Sebastian Theodore Ventrone
CPC分类号： G06F12/0862 , G06F9/461 , G06F2212/6024
摘要： According to the present invention, an anticipating cache memory loader is provided to "pre-load" the cache with the data and instructions most likely to be needed by the CPU once the currently executing task is completed or interrupted. The data and instructions most likely to be needed after the currently executing task is completed or executed is the same data and instructions that were loaded into the cache at the time the next scheduled task was last preempted or interrupted. By creating and storing an index to the contents of the cache for various tasks at the point in time the tasks are interrupted, the data and instructions previously swapped out of the cache can be retrieved from main memory and restored to the cache when needed. By using available bandwidth to pre-load the cache for the next scheduled task, the CPU can begin processing the next scheduled task more quickly and efficiently than if the present invention were not utilized. Using the present invention, CPU stalls will be reduced because the CPU will operate more efficiently without waiting for excessive periods of time for the cache to be loaded with relevant data and instructions.
摘要翻译： 根据本发明，提供一种预期的高速缓存存储器加载器，用于在当前执行的任务完成或中断之后，用CPU最有可能需要的数据和指令来“预加载”高速缓存。 在完成或执行当前执行任务之后最可能需要的数据和指令是在下一个计划任务最后被抢占或中断时加载到缓存中的相同数据和指令。 通过在任务中断的时间点为各种任务创建和存储索引到高速缓存的内容，可以从主存储器中检索先前从高速缓存交换的数据和指令，并在需要时将其还原到高速缓存。 通过使用可用带宽来预加载用于下一个计划任务的高速缓存，与不利用本发明相比，CPU可以更快速和有效地开始处理下一个计划的任务。 使用本发明，CPU停止将被减少，因为CPU将更有效地操作而不用等待超时间段来缓存相关数据和指令。
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公开(公告)号：US08037337B2
公开(公告)日：2011-10-11
申请号：US11946096
申请日：2007-11-28
IPC分类号： G06F1/04
CPC分类号： G06F1/06 , G06F1/08 , G06F9/3869
摘要： A design structure including a digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.
摘要翻译： 包括数字系统的设计结构。 数字系统包括（a）第一逻辑电路和第二逻辑电路，（b）第一寄存器，（c）第二寄存器，（d）第三寄存器，（e）时钟发生器电路，以及（f） 一个控制器电路。 第一逻辑电路能够获得第一数据并发送第二数据。 第二逻辑电路能够获得第二数据并发送第三数据。 时钟发生器电路能够在第一时间点断言（i）第一寄存器时钟信号，（ii）在第二时间点的第二寄存器时钟信号，以及（iii）第三时间点的第三寄存器时钟信号 。 控制器电路能够（i）确定第四时间点，（ii）确定第五时间点，（iii）控制时钟发生器电路以断言第二寄存器时钟信号。
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23.发明授权公开(公告)号：US07715995B2
公开(公告)日：2010-05-11
申请号：US12046501
申请日：2008-03-12
申请人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Nitin Sharma , Sebastian Theodore Ventrone , Charles S. Woodruff
发明人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Nitin Sharma , Sebastian Theodore Ventrone , Charles S. Woodruff
IPC分类号： G06F19/00
CPC分类号： G01R31/31721
摘要： An design structure for measuring power consumed during operation of an integrated circuit. The design structure including: a data processing circuit having an input and an output, the data processing circuit configured to generate an output data signal on based on an input data signal; a power measurement circuit configured to measure an amount of electrical power consumed by the processing circuit in generating the output signal from the input signal, the power measurement circuit connected between the processing circuit and a power supply for the processing circuit; and a memory element configured to store a tag containing a value representing the amount of electrical power consumed by the processing circuit in generating the output data signal from the input data signal and either (a) the input data of the input data signal or (b) a pointer to the input data of the input data signal.
摘要翻译： 一种用于测量集成电路运行期间消耗的功率的设计结构。 该设计结构包括：具有输入和输出的数据处理电路，所述数据处理电路被配置为基于输入数据信号产生输出数据信号; 功率测量电路，被配置为测量由所述输入信号产生所述输出信号时由所述处理电路消耗的电力量;连接在所述处理电路和所述处理电路的电源之间的功率测量电路; 以及存储元件，被配置为存储包含表示由处理电路消耗的电力量的值的标签，用于从输入数据信号生成输出数据信号，以及（a）输入数据信号的输入数据或（b ）指向输入数据信号的输入数据的指针。
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公开(公告)号：US20090157334A1
公开(公告)日：2009-06-18
申请号：US11956836
申请日：2007-12-14
申请人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Nitin Sharma , Sebastian Theodore Ventrone , Charles S. Woodruff
发明人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Nitin Sharma , Sebastian Theodore Ventrone , Charles S. Woodruff
CPC分类号： H03K19/0008 , G01R31/318575
摘要： An apparatus and method for measuring power consumed during operation of an integrated circuit. The apparatus including: a data processing circuit having an input and an output, the data processing circuit configured to generate an output data signal on based on an input data signal; a power measurement circuit configured to measure an amount of electrical power consumed by the processing circuit in generating the output signal from the input signal, the power measurement circuit connected between the processing circuit and a power supply for the processing circuit; and a memory element configured to store a tag containing a value representing the amount of electrical power consumed by the processing circuit in generating the output data signal from the input data signal and either (a) the input data of the input data signal or (b) a pointer to the input data of the input data signal.
摘要翻译： 一种用于测量集成电路操作期间消耗的功率的装置和方法。 该装置包括：具有输入和输出的数据处理电路，该数据处理电路被配置为基于输入数据信号产生一个输出数据信号; 功率测量电路，被配置为测量由所述输入信号产生所述输出信号时由所述处理电路消耗的电力量;连接在所述处理电路和所述处理电路的电源之间的功率测量电路; 以及存储元件，被配置为存储包含表示由处理电路消耗的电力量的值的标签，用于从输入数据信号生成输出数据信号，以及（a）输入数据信号的输入数据或（b ）指向输入数据信号的输入数据的指针。
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公开(公告)号：US07317348B2
公开(公告)日：2008-01-08
申请号：US11275773
申请日：2006-01-27
IPC分类号： H03K5/00
CPC分类号： G06F1/04 , H03K5/1504 , H03K19/00361
摘要： A digital system and a method for operating the same. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.
摘要翻译： 数字系统及其操作方法。 数字系统包括（a）第一逻辑电路和第二逻辑电路，（b）第一寄存器，（c）第二寄存器，（d）第三寄存器，（e）时钟发生器电路，以及（f） 一个控制器电路。 第一逻辑电路能够获得第一数据并发送第二数据。 第二逻辑电路能够获得第二数据并发送第三数据。 时钟发生器电路能够在第一时间点断言（i）第一寄存器时钟信号，（ii）在第二时间点的第二寄存器时钟信号，以及（iii）第三时间点的第三寄存器时钟信号 。 控制器电路能够（i）确定第四时间点，（ii）确定第五时间点，（iii）控制时钟发生器电路以断言第二寄存器时钟信号。
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公开(公告)号：US06934656B2
公开(公告)日：2005-08-23
申请号：US10605884
申请日：2003-11-04
CPC分类号： G06F11/261
摘要： A method and system for identifying logic function areas, which make up a virtual machine, that are affected by specific testcases. A Hardware Descriptor Language (HDL) is used to create a software model of the virtual machine. A simulator compiles and analyzes the HDL model, and creates a matrix scoreboard identifying logic function areas in the virtual machine. A complete list of testcases is run on the virtual machine while a monitor correlates each testcase with affected logic function areas to fill in the matrix scoreboard. When a subsequent test failure occurs, either because of a modification to a logic function area, or the execution of a new test, all logic function areas that are affected, either directly or indirectly, are identified.
摘要翻译： 用于识别构成虚拟机的逻辑功能区域受到特定测试用例影响的方法和系统。 硬件描述符语言（HDL）用于创建虚拟机的软件模型。 模拟器编译和分析HDL模型，并创建一个标识虚拟机中逻辑功能区域的矩阵记分板。 测试用例的完整列表在虚拟机上运行，而监视器将每个测试用例与受影响的逻辑功能区域相关联，以填充矩阵记分板。 当随后的测试失败发生时，由于对逻辑功能区域的修改或新测试的执行，所有被直接或间接影响的逻辑功能区域都被识别。
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27.发明授权Managing VT for reduced power using power setting commands in the instruction stream 失效使用指令流中的电源设置命令管理VT以降低功耗公开(公告)号：US06477654B1
公开(公告)日：2002-11-05
申请号：US09287159
申请日：1999-04-06
IPC分类号： G06F132
CPC分类号： G06F9/30083 , G06F1/3203 , G06F1/3243 , G06F1/3287 , G06F1/329 , G06F1/3296 , G06F8/4432 , G06F9/3867 , Y02D10/152 , Y02D10/171 , Y02D10/172 , Y02D10/24 , Y02D10/41
摘要： An integrated circuit includes a plurality of functional units which are capable of operating at more than one power/performance level and a power control unit. The power control unit controls the power/performance consumption of the different functional units to optimize operation of the integrated circuit. Special power control instructions are added to user applications in order to control via the power control unit, the power consumption of the different functional units.
摘要翻译： 集成电路包括能够以多于一个功率/性能水平操作的多个功能单元和功率控制单元。 功率控制单元控制不同功能单元的功率/性能消耗，以优化集成电路的运行。 特殊功率控制指令被添加到用户应用中，以通过功率控制单元控制不同功能单元的功耗。
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公开(公告)号：US06425109B1
公开(公告)日：2002-07-23
申请号：US09360384
申请日：1999-07-23
IPC分类号： G06F1750
CPC分类号： G06F17/5045
摘要： A system and method for interconnecting a plurality of cores into a single functional core. The method involves creating for each core a pin configuration structure based on a set of configuration rules. When the cores to be interconnected are selected, the pin configuration structure is accessed by the configurator program tool of the present invention. The configurator program tool then connects the cores together using the pin configuration structure and configuration rules for the selected cores. The configurator program tool generates an error-free high level model of the interconnected cores. The configurator program tool allows configuration flexibility and is general enough to handle most configuration scenarios. The tool is also easy to code, extensible, and can be applied to existing core designs with no modification of the cores themselves.
摘要翻译： 一种用于将多个核心互连成单个功能核心的系统和方法。 该方法包括基于一组配置规则为每个核心创建引脚配置结构。 当选择要互连的芯时，通过本发明的配置程序工具访问引脚配置结构。 然后，配置程序工具使用所选核心的引脚配置结构和配置规则将内核连接在一起。 配置程序工具生成互连核心的无错误高级模型。 配置程序工具允许配置灵活性，并且足以处理大多数配置场景。 该工具也易于编码，可扩展，并且可以应用于现有的核心设计，而不改变内核本身。
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公开(公告)号：US5986962A
公开(公告)日：1999-11-16
申请号：US121232
申请日：1998-07-23
IPC分类号： G11C11/413 , G11C14/00 , G11C11/40
CPC分类号： G11C14/00 , G11C11/413
摘要： An integrated circuit implements simple and efficient normal power to low power and low power to normal power transitions. Dedicated shadow latch circuits are added, each having a corresponding system latch. The state of the system latches is transferred to the shadow latches upon a transition from normal to low power mode and the stored information is transferred back to the system latches on the transition from low power to normal power operation. The shadow latches are optimized to minimize power usage during low power operation.
摘要翻译： 集成电路实现简单而有效的正常功率到低功率和低功率到正常功率转换。 添加专用的阴影锁存电路，每个都具有相应的系统锁存器。 系统锁存器的状态在从正常模式转换到低功耗模式时被传送到阴影锁存器，并且存储的信息从低功耗转换到正常工作状态转换回系统锁存器。 阴影锁存器被优化以在低功率操作期间最小化功率使用。
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30.发明授权Apparatus and method for prefetching data based on information contained in a compiler generated program map 失效基于编译器生成的程序映射中包含的信息来预取数据的装置和方法
公开(公告)号：US5918246A
公开(公告)日：1999-06-29
申请号：US788870
申请日：1997-01-23
申请人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Wilbur David Pricer , Sebastian Theodore Ventrone
发明人： Kenneth Joseph Goodnow , Clarence Rosser Ogilvie , Wilbur David Pricer , Sebastian Theodore Ventrone
CPC分类号： G06F8/4442 , G06F12/0862 , G06F2212/6028
摘要： An apparatus and method for pre-loading a cache memory based on information contained in a compiler generated program map are disclosed. The program map is generated by the compiler at the time source code is compiled into object code. For each application program, the user would have this program map stored with the object file. At the beginning of the program execution cycle, the operating system will determine whether or not a program map exists for the application. If a program map exists, the operating system will load the program map into an area of RAM designated as the program map random access memory (RAM). The program map will be used to pre-load the cache with the appropriate data and instructions for the central processing unit (CPU) to process. The program mapping would be the address location of each jump/branch target that the CPU might encounter during the execution cycle. Each of these locations represent a starting point for a new code sequence. At the start of the map will be an identifier field to mark the start of the map. The next field in the program map will provide the entry point of the starting address of the application program. If a particular application program does not have a program map, the program and cache operation will remain unchanged. This feature provides backwards compatibility with existing application programs.
摘要翻译： 公开了一种基于编译器生成的程序映射中包含的信息来预加载高速缓冲存储器的装置和方法。 程序地图由编译器在源代码被编译成目标代码时生成。 对于每个应用程序，用户将该目录文件存储该程序映射。 在程序执行周期开始时，操作系统将确定应用程序是否存在程序映射。 如果存在程序映射，则操作系统将程序映射加载到指定为程序映射随机存取存储器（RAM）的RAM区域中。 程序地图将用于预先加载高速缓存，并具有相应的数据和指令，供中央处理单元（CPU）处理。 程序映射将是执行周期中CPU可能遇到的每个跳转/转移目标的地址位置。 这些位置中的每一个代表新代码序列的起始点。 在地图的开始，将是一个标识符字段来标记地图的开始。 程序地图中的下一个字段将提供应用程序起始地址的入口点。 如果特定的应用程序没有程序映射，程序和缓存操作将保持不变。 此功能提供与现有应用程序的向后兼容性。
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