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31 条记录 (耗时 0.041 秒)

    High level automatic core configuration
    1.
    发明授权
    High level automatic core configuration 有权
    高级自动核心配置

    公开(公告)号：US06425109B1

    公开(公告)日：2002-07-23

    申请号：US09360384

    申请日：1999-07-23

    申请人： Charles N. Choukalos ,  Alvar Antonio Dean ,  Scott Alan Tetreault ,  Sebastian Theodore Ventrone

    发明人： Charles N. Choukalos ,  Alvar Antonio Dean ,  Scott Alan Tetreault ,  Sebastian Theodore Ventrone

    IPC分类号： G06F1750

    CPC分类号： G06F17/5045

    摘要： A system and method for interconnecting a plurality of cores into a single functional core. The method involves creating for each core a pin configuration structure based on a set of configuration rules. When the cores to be interconnected are selected, the pin configuration structure is accessed by the configurator program tool of the present invention. The configurator program tool then connects the cores together using the pin configuration structure and configuration rules for the selected cores. The configurator program tool generates an error-free high level model of the interconnected cores. The configurator program tool allows configuration flexibility and is general enough to handle most configuration scenarios. The tool is also easy to code, extensible, and can be applied to existing core designs with no modification of the cores themselves.

    摘要翻译： 一种用于将多个核心互连成单个功能核心的系统和方法。 该方法包括基于一组配置规则为每个核心创建引脚配置结构。 当选择要互连的芯时，通过本发明的配置程序工具访问引脚配置结构。 然后，配置程序工具使用所选核心的引脚配置结构和配置规则将内核连接在一起。 配置程序工具生成互连核心的无错误高级模型。 配置程序工具允许配置灵活性，并且足以处理大多数配置场景。 该工具也易于编码，可扩展，并且可以应用于现有的核心设计，而不改变内核本身。

    Stacked voltage rails for low-voltage DC distribution
    2.
    发明授权
    Stacked voltage rails for low-voltage DC distribution 失效
    用于低压直流分配的堆叠电压轨

    公开(公告)号：US06479974B2

    公开(公告)日：2002-11-12

    申请号：US09750884

    申请日：2000-12-28

    申请人： John Maxwell Cohn ,  Alvar Antonio Dean ,  David James Hathaway ,  Patrick Edward Perry ,  Sebastian Theodore Ventrone

    发明人： John Maxwell Cohn ,  Alvar Antonio Dean ,  David James Hathaway ,  Patrick Edward Perry ,  Sebastian Theodore Ventrone

    IPC分类号： G05F304

    CPC分类号： H01L23/5286 ,  H01L2924/0002 ,  H01L2924/00

    摘要： A system and method for providing on-chip voltage distribution and regulation. In accordance with the system of the present invention, an IC chip includes a source voltage plane having a source supply rail for supplying power to the IC chip and a source ground rail for sinking power supplied therefrom. At least one intermediate ground rail is connected between the source supply rail and the source ground rail to divide the source voltage plane into multiple intermediate voltage planes. The intermediate ground rail serves as a supply rail for a subsequent intermediate voltage plane such that the intermediate voltage planes are series-connected.

    摘要翻译： 一种用于提供片上电压分配和调节的系统和方法。 根据本发明的系统，IC芯片包括具有用于向IC芯片供电的源极电源轨的源极电压平面和用于从其供电的电力的源极接地导轨。 至少一个中间接地轨连接在源电源轨和源极接地轨之间，以将源电压平面分成多个中间电压平面。 中间接地导轨用作后续中间电压平面的电源轨，使得中间电压平面串联连接。

    Method and system for optimizing code using an optimizing coprocessor
    8.
    发明授权
    Method and system for optimizing code using an optimizing coprocessor 失效
    使用优化协处理器优化代码的方法和系统

    公开(公告)号：US06820254B2

    公开(公告)日：2004-11-16

    申请号：US09681327

    申请日：2001-03-19

    申请人： Jack Robert Smith ,  Sebastian Theodore Ventrone

    发明人： Jack Robert Smith ,  Sebastian Theodore Ventrone

    IPC分类号： G06F945

    CPC分类号： G06F8/443

    摘要： A data processing system includes a central processing unit (CPU) in communication with a system memory. Within the system memory, there is stored legacy code that does not utilize the full features of the CPU. The data processing system also includes a code-optimizing coprocessor in communication with the CPU and the system memory. Control logic within the code-optimizing coprocessor causes the code-optimizing coprocessor to generate optimized code from the legacy code at the same time the CPU executes the legacy code, such that the optimized code is tailored according to the CPU. After the code-optimizing coprocessor has generated at least some optimized code, the code-optimizing coprocessor causes the CPU to automatically utilize at least some optimized code in lieu of at least some of the legacy code.

    摘要翻译： 数据处理系统包括与系统存储器通信的中央处理单元（CPU）。 在系统内存中，存储了不利用CPU全部功能的旧版代码。 数据处理系统还包括与CPU和系统存储器通信的代码优化协处理器。 代码优化协处理器内的控制逻辑使得代码优化协处理器在CPU执行遗留代码的同时从旧代码生成优化的代码，使得优化的代码根据CPU进行调整。 在代码优化协处理器已经生成了至少一些优化的代码之后，代码优化协处理器使CPU自动利用至少一些优化的代码来代替至少一些遗留代码。

    DESIGN STRUCTURES INCLUDING CIRCUITS FOR NOISE REDUCTION IN DIGITAL SYSTEMS
    9.
    发明申请
    DESIGN STRUCTURES INCLUDING CIRCUITS FOR NOISE REDUCTION IN DIGITAL SYSTEMS 有权
    设计结构包括数字系统中减少噪声的电路

    公开(公告)号：US20090138676A1

    公开(公告)日：2009-05-28

    申请号：US11946096

    申请日：2007-11-28

    申请人： Nancy H. Pratt ,  Sebastian Theodore Ventrone

    发明人： Nancy H. Pratt ,  Sebastian Theodore Ventrone

    IPC分类号： G06F15/76 ,  G06F9/30

    CPC分类号： G06F1/06 ,  G06F1/08 ,  G06F9/3869

    摘要： A design structure including a digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.

    摘要翻译： 包括数字系统的设计结构。 数字系统包括（a）第一逻辑电路和第二逻辑电路，（b）第一寄存器，（c）第二寄存器，（d）第三寄存器，（e）时钟发生器电路，以及（f） 一个控制器电路。 第一逻辑电路能够获得第一数据并发送第二数据。 第二逻辑电路能够获得第二数据并发送第三数据。 时钟发生器电路能够在第一时间点断言（i）第一寄存器时钟信号，（ii）在第二时间点的第二寄存器时钟信号，以及（iii）第三时间点的第三寄存器时钟信号 。 控制器电路能够（i）确定第四时间点，（ii）确定第五时间点，（iii）控制时钟发生器电路以断言第二寄存器时钟信号。

    Noise reduction in digital systems when the noise is caused by simultaneously clocking data registers
    10.
    发明授权
    Noise reduction in digital systems when the noise is caused by simultaneously clocking data registers 失效
    数字系统噪声降低时，噪声是由数据寄存器同步引起的

    公开(公告)号：US07463083B2

    公开(公告)日：2008-12-09

    申请号：US11937559

    申请日：2007-11-09

    申请人： Nancy H. Pratt ,  Sebastian Theodore Ventrone

    发明人： Nancy H. Pratt ,  Sebastian Theodore Ventrone

    IPC分类号： H03K5/00

    CPC分类号： G06F1/04 ,  H03K5/1504 ,  H03K19/00361

    摘要： A digital system. The digital system includes (a) a first logic circuit and a second logic circuit, (b) a first register, (c) a second register, (d) a third register, (e) a clock generator circuit, and (f) a controller circuit. The first logic circuit is capable of obtaining first data and sending second data. The second logic circuit is capable of obtaining the second data and sending third data. The clock generator circuit is capable of asserting (i) a first register clock signal at a first time point, (ii) a second register clock signal at a second time point, and (iii) a third register clock signal at a third time point. The controller circuit is capable of (i) determining a fourth time point, (ii) determining a fifth time point, (iii) controlling the clock generator circuit to assert the second register clock signal.

    摘要翻译： 数字系统 数字系统包括（a）第一逻辑电路和第二逻辑电路，（b）第一寄存器，（c）第二寄存器，（d）第三寄存器，（e）时钟发生器电路，以及（f） 一个控制器电路。 第一逻辑电路能够获得第一数据并发送第二数据。 第二逻辑电路能够获得第二数据并发送第三数据。 时钟发生器电路能够在第一时间点断言（i）第一寄存器时钟信号，（ii）在第二时间点的第二寄存器时钟信号，以及（iii）第三时间点的第三寄存器时钟信号 。 控制器电路能够（i）确定第四时间点，（ii）确定第五时间点，（iii）控制时钟发生器电路以断言第二寄存器时钟信号。