公开(公告)号：US10909289B2

公开(公告)日：2021-02-02

申请号：US16419734

申请日：2019-05-22

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari ,  Iain Singleton

IPC: G06F30/3323 ,  G06F30/33 ,  G06F11/07 ,  G06F11/30 ,  G06F9/30 ,  G06F9/38 ,  G06F30/333

Abstract: A hardware monitor arranged to detect livelock in a hardware design for an integrated circuit. The hardware monitor includes monitor and detection logic configured to detect when a particular state has occurred in an instantiation of the hardware design; and assertion evaluation logic configured to periodically evaluate one or more assertions that assert a formal property related to reoccurrence of the particular state in the instantiation of the hardware design to detect whether the instantiation of the hardware design is in a livelock comprising the predetermined state. The hardware monitor may be used by a formal verification tool to exhaustively verify that the instantiation of the hardware design cannot enter a livelock comprising the predetermined state.

公开(公告)号：US10210119B2

公开(公告)日：2019-02-19

申请号：US15454100

申请日：2017-03-09

Applicant: Imagination Technologies Limited

Inventor： Iain Singleton ,  Ashish Darbari ,  John Alexander Osborne Netterville

IPC: G06F9/455 ,  G06F17/50 ,  G06F13/364 ,  G06F13/16 ,  G06F13/362 ,  G06F13/42

Abstract: Operation of an arbiter in a hardware design is verified. The arbiter receives a plurality of requests over a plurality of clock cycles, including a monitored request and outputs the requests in priority order. The requests received by and output from the arbiter in each clock cycle are identified. The priority of the watched request relative to other pending requests in the arbiter is then tracked using a counter that is updated based on the requests input to and output from the arbiter in each clock cycle and a mask identifying the relative priority of requests received by the arbiter in the same clock cycle. The operation of the arbiter is verified using an assertion which establishes a relationship between the counter and the clock cycle in which the watched request is output from the arbiter.

公开(公告)号：US10083262B2

公开(公告)日：2018-09-25

申请号：US15689021

申请日：2017-08-29

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari ,  Colin McKellar

IPC: G06F9/455 ,  G06F17/50

Abstract: Methods and systems for detecting deadlock in a hardware design. The method comprises identifying one or more control signals in the hardware design; generating a state machine for each of the one or more control signals to track the state of the control signal; generating one or more assertions for each control signal to detect that the control signal is in a deadlock state from the state machine; and detecting whether any of the one or more control signal are in a deadlock state using the assertions. The method may also comprise generating one or more fairness constraints to impose on a particular assertion and detecting the particular control signal is in the deadlock state using the assertions under the fairness constraints.

公开(公告)号：US20170357742A1

公开(公告)日：2017-12-14

申请号：US15689021

申请日：2017-08-29

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari ,  Colin McKellar

IPC: G06F17/50

CPC classification number: G06F17/5009 ,  G06F9/524 ,  G06F11/3608 ,  G06F17/5022 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/505 ,  G06F2217/06

Abstract: Methods and systems for detecting deadlock in a hardware design. The method comprises identifying one or more control signals in the hardware design; generating a state machine for each of the one or more control signals to track the state of the control signal; generating one or more assertions for each control signal to detect that the control signal is in a deadlock state from the state machine; and detecting whether any of the one or more control signal are in a deadlock state using the assertions. The method may also comprise generating one or more fairness constraints to impose on a particular assertion and detecting the particular control signal is in the deadlock state using the assertions under the fairness constraints.

公开(公告)号：US09767236B2

公开(公告)日：2017-09-19

申请号：US14674651

申请日：2015-03-31

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari ,  Colin McKellar

IPC: G06F9/455 ,  G06F17/50

CPC classification number: G06F17/5009 ,  G06F9/524 ,  G06F11/3608 ,  G06F17/5022 ,  G06F17/504 ,  G06F17/5045 ,  G06F17/505 ,  G06F2217/06

Abstract: Methods and systems for detecting deadlock in a hardware design. The method comprises identifying one or more control signals in the hardware design; generating a state machine for each of the one or more control signals to track the state of the control signal; generating one or more assertions for each control signal to detect that the control signal is in a deadlock state from the state machine; and detecting whether any of the one or more control signal are in a deadlock state using the assertions. The method may also comprise generating one or more fairness constraints to impose on a particular assertion and detecting the particular control signal is in the deadlock state using the assertions under the fairness constraints.

公开(公告)号：US20170220707A1

公开(公告)日：2017-08-03

申请号：US15340816

申请日：2016-11-01

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari

IPC: G06F17/50

CPC classification number: G06F17/504 ,  G06F17/5022 ,  G06F17/505 ,  G06F2217/06 ,  G06F2217/12

Abstract: A method of detecting a bug in a counter of a hardware design that includes formally verifying, using a formal verification tool, an inductive assertion from a non-reset state of an instantiation of the hardware design. The inductive assertion establishes a relationship between the counter and a test bench counter at two or more points in time. If the formal verification tool identifies at least one valid state of an instantiation of the counter in which the inductive assertion is not true, information is output indicating a location of a bug in the hardware design or the test bench counter.

公开(公告)号：US20240411972A1

公开(公告)日：2024-12-12

申请号：US18807813

申请日：2024-08-16

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari ,  Iain Singleton

IPC: G06F30/3323 ,  G06F11/07 ,  G06F11/34 ,  G06F30/39

Abstract: A formal verification tool used with a hardware monitor to verify that a hardware design for an electronic device does not comprise a bug or error that can cause an instantiation of the hardware design to fetch an instruction from an out-of-bounds address. Formal assertations for a hardware design are received, wherein the formal assertions assert a formal property that compares a memory address from which an instruction was fetched by an instantiation of the hardware design to an allowable memory address range or an unallowable memory address range associated with an operating state of the instantiation of the hardware design when the fetch was performed. The tool formally verifies that the formal assertations are true for the hardware design to identify whether the hardware design has a bug or error that causes an out-of-bounds violation.

公开(公告)号：US20240311487A1

公开(公告)日：2024-09-19

申请号：US18669262

申请日：2024-05-20

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari

IPC: G06F21/57 ,  G06F21/51

CPC classification number: G06F21/572 ,  G06F21/51 ,  G06F2221/033

Abstract: Described herein are hardware monitors arranged to detect illegal firmware instructions in a firmware binary image using a hardware design and one or more formal assertions. The hardware monitors include monitor and detection logic configured to detect when an instantiation of the hardware design has started and/or stopped execution of the firmware and to detect when the instantiation of the hardware design has decoded an illegal firmware instruction. The hardware monitors also include assertion evaluation logic configured to determine whether the firmware binary image comprises an illegal firmware instruction by evaluating one or more assertions that assert that if a stop of firmware execution has been detected, that a decode of an illegal firmware instruction has (or has not) been detected. The hardware monitor may be used by a formal verification tool to exhaustively verify that the firmware boot image does not comprise an illegal firmware instruction, or during simulation to detect illegal firmware instructions in a firmware boot image.

公开(公告)号：US20230094774A1

公开(公告)日：2023-03-30

申请号：US18076231

申请日：2022-12-06

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari ,  Iain Singleton

IPC: G06F30/3323 ,  G06F11/36 ,  G06F11/34 ,  G06F30/39 ,  G06F30/30 ,  G06F11/30 ,  G06F119/18

Abstract: A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.

公开(公告)号：US20210182463A1

公开(公告)日：2021-06-17

申请号：US17184186

申请日：2021-02-24

Applicant: Imagination Technologies Limited

Inventor： Ashish Darbari ,  Iain Singleton

IPC: G06F30/3323 ,  G06F11/30 ,  G06F11/34 ,  G06F11/36 ,  G06F30/30 ,  G06F30/39

Abstract: A hardware monitor arranged to assess performance of a hardware design for an integrated circuit to complete a task. The hardware monitor includes monitoring and counting logic configured to count a number of cycles between start and completion of the symbolic task in the hardware design; and property evaluation logic configured to evaluate one or more formal properties related to the counted number of cycles to assess the performance of the hardware design in completing the symbolic task. The hardware monitor may be used by a formal verification tool to exhaustively verify that the hardware design meets a desired performance goal and/or to exhaustively identify a performance metric (e.g. best case and/or worst case performance) with respect to completion of the task.