公开(公告)号：US11121731B2

公开(公告)日：2021-09-14

申请号：US16550574

申请日：2019-08-26

Applicant: Intel Corporation

Inventor： Ashoke Ravi ,  Benjamin Jann ,  Satwik Patnaik ,  Elan Banin ,  Igal Kushnir ,  Ofir Degani ,  Alexandros Margomenos

IPC: H04B1/04 ,  H03L7/24 ,  G01R27/06 ,  H01Q3/40

Abstract: Techniques are described related to digital radio control and operation. The various techniques described herein enable high-frequency local oscillator (LO) signal generation using injection locked cock multipliers (ILCMs). The techniques also include the use of LO signals for carrier aggregation applications for phased array front ends. Furthermore, the disclosed techniques include the use of array element-level control using per-chain DC-DC converters. Still further, the disclosed techniques include the use of adaptive spatial filtering and optimal combining of analog-to-digital converters (ADCs) to maximize dynamic range in digital beamforming systems.

公开(公告)号：US20210116871A1

公开(公告)日：2021-04-22

申请号：US16500172

申请日：2017-06-26

Applicant: Intel Corporation

Inventor： Sarit Zur ,  Igal Kushnir ,  Gil Horovitz ,  Rotem Banin ,  Sergey Bershansky

IPC: G04F10/00 ,  G04F10/06 ,  H03L7/197 ,  H03L7/187

Abstract: A frequency estimator for estimating a frequency, including a counter configured to count an integer number of full clock cycles during a measurement time window; a Time-to-Digital Converter (TDC) configured to measure a fraction of a clock cycle during the measurement time window; and a processor configured to determine the estimated frequency based on the counted number of full clock cycles and the measured fraction of the clock cycle.

公开(公告)号：US20200287557A1

公开(公告)日：2020-09-10

申请号：US16292717

申请日：2019-03-05

Applicant: Intel Corporation

Inventor： Gil Horovitz ,  Sharon Malevsky ,  Evgeny Shumaker ,  Igal Kushnir

IPC: H03L7/099 ,  H04B1/00

Abstract: Systems, methods, and circuitries are provided to generate a radio frequency (RF) signal having a desired radio frequency fRF. In one example a frequency synthesizer system includes a clock, an opportunistic phase locked loop (PLL), and an RF PLL. The clock circuitry is configured to generate a clock signal having a frequency fXTL. The opportunistic phase locked loop (PLL) is configured to generate a reference signal having a reference frequency fREF that is close to a free-running frequency of an oscillator in the opportunistic PLL. The opportunistic PLL is configured to synchronize the reference signal to the clock signal. The RF PLL is configured to generate the RF signal having the desired radio frequency and to synchronize the RF signal with the reference signal.

公开(公告)号：US10693687B1

公开(公告)日：2020-06-23

申请号：US16367548

申请日：2019-03-28

Applicant: Intel Corporation

Inventor： Igal Kushnir

IPC: H04B1/04 ,  H04L27/00 ,  H04L25/03 ,  H04B7/0413

Abstract: Techniques are disclosed implementing a radio partitioning architecture using multiple data streams over a single coaxial cable that does not require external RF filtering. This provides a flexible frequency scheme (e.g., using IF frequency adjustment) that enables the avoidance of Wi-Fi and LTE harmonics. The techniques include leveraging baseband filtering, which may be integrated with the radio head in a common radio frequency intergraded circuit (RFIC).

公开(公告)号：US20180091180A1

公开(公告)日：2018-03-29

申请号：US15275779

申请日：2016-09-26

Applicant: Intel Corporation

Inventor： Igal Kushnir ,  Gil Horovitz ,  Sarit Zur

IPC: H04B1/38 ,  H04B17/11

CPC classification number: H04B1/38 ,  H03B21/00 ,  H03B21/01 ,  H03L7/08 ,  H03L7/099 ,  H03L2207/06 ,  H04B17/11 ,  H04L27/205

Abstract: Control circuitry for use in generating a local oscillator (LO) signal is provided. Synthesizer control circuitry is configured to control synthesizer circuitry to generate an analog oscillator signal having a first frequency at which phase noise is minimized. DS control circuitry is configured to generate a control word or message to cause DS circuitry to generate a digital DS signal having a desired frequency when the DS circuitry is clocked by the oscillator signal having the first frequency. The desired frequency is proportional to the LO signal frequency. The digital DS signal generated by the DS circuitry is used to generate the LO signal. Thus the first frequency used to clock the DS circuitry is selected to optimize the oscillator rather than having some relationship to the LO frequency. In addition, a single synthesizer may be used in order to simultaneously generate many LO signals.