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公开(公告)号：US11824576B2
公开(公告)日：2023-11-21
申请号：US17030832
申请日：2020-09-24
Applicant: Intel Corporation
Inventor： Ofir Degani , Gil Horovitz , Evgeny Shumaker , Sergey Bershansky , Aryeh Farber , Igor Gertman , Run Levinger
Abstract: An apparatus for generating an output oscillator signal is provided. The apparatus includes a deviation determining circuitry configured to generate a deviation signal based on a first comparison signal and a second comparison signal. Further, the apparatus includes a first oscillator configured to generate the output oscillator signal based on the deviation signal and a second oscillator signal from a second, resonator-based oscillator. The first comparison signal is based on the second oscillator signal or the output oscillator signal. The second oscillator signal has a frequency of at least 1 GHz. The second comparison signal is based on a third oscillator signal from a third oscillator. The third oscillator signal has a frequency lower than 1 GHz.
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公开(公告)号：US11923859B2
公开(公告)日：2024-03-05
申请号：US17033122
申请日：2020-09-25
Applicant: Intel Corporation
Inventor： Evgeny Shumaker , Sergey Bershansky , Ofir Degani , Run Levinger
CPC classification number: H03L7/085 , G04F10/005 , H03M1/50
Abstract: An apparatus for generating a frequency estimate of an output signal includes a reference signal generator configured to generate a reference clock signal. The apparatus includes frequency estimation circuitry configured to generate a cycle count based frequency estimation of the output signal based on the reference clock signal and a clock cycle count of the output signal. The frequency estimation circuitry further generates a fractional frequency estimation of the output signal based on the reference clock signal and a plurality of time-to-digital conversion phase samples of the output signal. The frequency estimation circuitry further generates the frequency estimate of the output signal using the cycle count based frequency estimation within a range and a frequency error determined from the fractional frequency estimation. The plurality of time-to-digital conversion phase samples and the cycle count based frequency estimation use a same number of reference clock cycles of the reference clock signal.
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公开(公告)号：US11237195B2
公开(公告)日：2022-02-01
申请号：US16500172
申请日：2017-06-26
Applicant: Intel Corporation
Inventor： Sarit Zur , Igal Kushnir , Gil Horovitz , Rotem Banin , Sergey Bershansky
Abstract: A frequency estimator for estimating a frequency, including a counter configured to count an integer number of full clock cycles during a measurement time window; a Time-to-Digital Converter (TDC) configured to measure a fraction of a clock cycle during the measurement time window; and a processor configured to determine the estimated frequency based on the counted number of full clock cycles and the measured fraction of the clock cycle.
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公开(公告)号：US20210116871A1
公开(公告)日：2021-04-22
申请号：US16500172
申请日：2017-06-26
Applicant: Intel Corporation
Inventor： Sarit Zur , Igal Kushnir , Gil Horovitz , Rotem Banin , Sergey Bershansky
Abstract: A frequency estimator for estimating a frequency, including a counter configured to count an integer number of full clock cycles during a measurement time window; a Time-to-Digital Converter (TDC) configured to measure a fraction of a clock cycle during the measurement time window; and a processor configured to determine the estimated frequency based on the counted number of full clock cycles and the measured fraction of the clock cycle.
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