公开(公告)号：US20190324746A1

公开(公告)日：2019-10-24

申请号：US15957728

申请日：2018-04-19

Applicant: Intel Corporation

Inventor： SUBRAMANIAM MAIYURAN ,  GUEI-YUAN LUEH ,  SUPRATIM PAL ,  ASHUTOSH GARG ,  CHANDRA S. GURRAM ,  JORGE E. PARRA ,  JUNJIE GU ,  KONRAD TRIFUNOVIC ,  HONG BIN LIAO ,  MIKE B. MACPHERSON ,  SHUBH B. SHAH ,  SHUBRA MARWAHA ,  STEPHEN JUNKINS ,  TIMOTHY R. BAUER ,  VARGHESE GEORGE ,  WEIYU CHEN

IPC: G06F9/30 ,  G06F9/38 ,  G06T1/20

Abstract: Embodiments described herein provided for an instruction and associated logic to enable GPGPU program code to access special purpose hardware logic to accelerate dot product operations. One embodiment provides for a graphics processing unit comprising a fetch unit to fetch an instruction for execution and a decode unit to decode the instruction into a decoded instruction. The decoded instruction is a matrix instruction to cause the graphics processing unit to perform a parallel dot product operation. The GPGPU also includes a systolic dot product unit to execute the decoded instruction across one or more SIMD lanes using multiple systolic layers, wherein to execute the decoded instruction, a dot product computed at a first systolic layer is to be output to a second systolic layer, wherein each systolic layer includes one or more sets of interconnected multipliers and adders, each set of multipliers and adders to generate a dot product.

公开(公告)号：US20190073336A1

公开(公告)日：2019-03-07

申请号：US16103798

申请日：2018-08-14

Applicant: INTEL CORPORATION

Inventor： VARGHESE GEORGE ,  SANJEEV S. JAHAGIRDAR ,  DEBORAH T. MARR

IPC: G06F15/80 ,  G06F1/32 ,  G06F9/50 ,  G06F13/40

CPC classification number: G06F15/80 ,  G06F1/3206 ,  G06F1/3293 ,  G06F1/3296 ,  G06F9/5094 ,  G06F13/4022 ,  Y02D10/122 ,  Y02D10/151 ,  Y02D10/22

Abstract: A method is described that entails operating enabled cores of a multi-core processor such that both cores support respective software routines with a same instruction set, a first core being higher performance and consuming more power than a second core under a same set of applied supply voltage and operating frequency.

公开(公告)号：US20180129542A1

公开(公告)日：2018-05-10

申请号：US15672086

申请日：2017-08-08

Applicant: Intel Corporation

Inventor： SANJEEV S. JAHAGIRDAR ,  VARGHESE GEORGE ,  INDER M. SODHI

IPC: G06F9/50 ,  G06F9/30 ,  G06F9/48

Abstract: Some implementations provide techniques and arrangements to migrate threads from a first core of a processor to a second core of the processor. For example, some implementations may identify one or more threads scheduled for execution at a processor. The processor may include a plurality of cores, including a first core having a first characteristic and a second core have a second characteristic that is different than the first characteristic. Execution of the one or more threads by the first core may be initiated. A determination may be made whether to apply a migration policy. In response to determining to apply the migration policy, migration of the one or more threads from the first core to the second core may be initiated.