公开(公告)号：US20060089827A1

公开(公告)日：2006-04-27

申请号：US10970469

申请日：2004-10-21

申请人： Carol Gabele ,  Wolfgang Roesner ,  Derek Williams

发明人： Carol Gabele ,  Wolfgang Roesner ,  Derek Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： According to one method of simulation processing, instrumentation code, such as an runtime executive (rtx), receives one or more statements describing an count event and identifying the count event as an outlying count event. While simulating a design utilizing the HDL simulation model, occurrences of the outlying count event are counted to obtain a count event value. Simulation result data obtained from simulating the design is then received and processed. In the processing, the count event value is recorded within a data storage subsystem responsive to a determination of whether or not the count event value of the outlying count event exceeds a previously recorded count event value.

摘要翻译： 根据模拟处理的一种方法，诸如运行时执行程序（rtx）的仪器代码接收描述计数事件的一个或多个语句，并将计数事件识别为外部计数事件。 在使用HDL仿真模型模拟设计的同时，计算出外部计数事件以获得计数事件值。 然后接收并处理从模拟设计获得的仿真结果数据。 在处理中，响应于确定偏移计数事件的计数事件值是否超过先前记录的计数事件值，将计数事件值记录在数据存储子系统内。

公开(公告)号：US20060025978A1

公开(公告)日：2006-02-02

申请号：US10902628

申请日：2004-07-29

申请人： Wolfgang Roesner ,  Derek Williams

发明人： Wolfgang Roesner ,  Derek Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： Within a display device, a respective one of a plurality of design graphical representations is displayed for each of a plurality of hierarchically arranged design entity instances within a simulated system. The design entity instances include a particular design entity instance containing a latch that is represented by a particular design graphical representation. A configuration entity instance associated with the particular design entity is identified within a configuration database associated with the simulated system. The configuration entity instance has a plurality of different settings that each reflects a value of the latch. Within the display device, a configuration graphical representation of the configuration entity instance is presented in association with the particular design graphical representation corresponding to the particular design entity instance. In addition, a current setting of the configuration entity instance is presented concurrently with the configuration graphical representation.

摘要翻译： 在显示装置内，为模拟系统内的多个分层布置的设计实体实例中的每一个显示多个设计图形表示中的相应一个。 设计实体实例包括包含由特定设计图形表示表示的锁存器的特定设计实体实例。 在与模拟系统相关联的配置数据库中识别与特定设计实体相关联的配置实体实例。 配置实体实例具有多个不同的设置，每个设置反映锁存器的值。 在显示设备内，与对应于特定设计实体实例的特定设计图形表示相关联地呈现配置实体实例的配置图形表示。 此外，配置实体实例的当前设置与配置图形表示同时呈现。

公开(公告)号：US20050049740A1

公开(公告)日：2005-03-03

申请号：US10651186

申请日：2003-08-28

申请人： Wolfgang Roesner ,  Derek Williams

发明人： Wolfgang Roesner ,  Derek Williams

IPC分类号： G06F17/50 ,  G06F19/00

CPC分类号： G06F17/5045 ,  G06F17/5022

摘要： Methods, data processing systems, and program products supporting the insertion of clone latches within a digital design are disclosed. According to one method, a parent latch within the digital design is specified in an HDL statement in one of the HDL files representing a digital design. In addition, a clone latch is specified within the digital design utilizing an HDL clone latch declaration. An HDL attribute-value pair is associated with the HDL clone latch declaration to indicate a relationship between the clone latch and the parent latch according to which the clone latch is automatically set to a same value as the parent latch when the parent latch is set. Thereafter, when a configuration compiler receives one or more design intermediate files containing the clone latch declaration, the configuration compiler creates at least one data structure in a configuration database representing the clone latch and the relationship between the clone latch and the parent latch.

摘要翻译： 公开了支持在数字设计中插入克隆锁存器的方法，数据处理系统和程序产品。 根据一种方法，数字设计中的父锁存器在表示数字设计的HDL文件之一中的HDL语句中被指定。 此外，使用HDL克隆锁存器声明在数字设计中指定克隆锁存器。 HDL属性值对与HDL克隆锁存器声明相关联，以指示克隆锁存器和父锁存器之间的关系，根据该关系，克隆锁存器在父锁存器被置位时自动设置为与父锁存器相同的值。 此后，当配置编译器接收到包含克隆锁存器声明的一个或多个设计中间文件时，配置编译器在表示克隆锁存器的配置数据库中创建至少一个数据结构以及克隆锁存器和父锁存器之间的关系。

公开(公告)号：US20070260441A1

公开(公告)日：2007-11-08

申请号：US11382088

申请日：2006-05-08

申请人： Gabor Bobok ,  Wolfgang Roesner ,  Derek Williams

发明人： Gabor Bobok ,  Wolfgang Roesner ,  Derek Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022

摘要： According to a method of simulation processing, an instrumented simulation executable model of a design is built by compiling one or more hardware description language (HDL) files specifying one or more design entities within the design and one or more instrumentation entities and instantiating instances of the one or more instrumentation entities within instances of the one or more design entities. Operation of the design is then simulated utilizing the instrumented simulation executable model. Simulating operation includes each of multiple instantiations of the one or more instrumentation entities generating a respective external phase signal representing an occurrence of a particular phase of operation and instrumentation combining logic generating from external phase signals of the multiple instantiations of the one or more instrumentation entities an aggregate phase signal representing an occurrence of the particular phase.

摘要翻译： 根据模拟处理的方法，通过编译指定设计中的一个或多个设计实体的一个或多个硬件描述语言（HDL）文件和一个或多个设备实体和一个或多个设备实例的实例化来构建设计的仪器化模拟可执行模型 在一个或多个设计实体的实例内的一个或多个仪表实体。 然后使用仪器化模拟可执行模型对设计的操作进行模拟。 模拟操作包括一个或多个仪器实体的多个实例中的每个实例，其产生表示特定操作阶段的出现的相应的外部相位信号，以及组合从一个或多个仪器实体的多个实例的外部相位信号产生的逻辑 聚合相位信号表示特定相位的出现。

公开(公告)号：US20070050735A1

公开(公告)日：2007-03-01

申请号：US11552306

申请日：2006-10-24

申请人： Wolfgang Roesner ,  Derek Williams

发明人： Wolfgang Roesner ,  Derek Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/505

摘要： In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains first and second latches each having a respective plurality of different possible latch values. With one or more statements, a first Dial instance is associated with the first latch and a second Dial instance is associated with the second latch. A setting of the first Dial instance thus controls which of the plurality of different possible values is loaded in the first latch, and a setting of the second Dial instance controls which of the plurality of different possible values is loaded in the second latch. With a statement, a Register instance is concurrently associated with both the first and the second latches, such that a setting of the Register instance controls the latch values loaded in both the first and second latches.

摘要翻译： 在至少一个硬件定义语言（HDL）文件中，指定包含数字系统的功能部分的至少一个设计实体。 设计实体逻辑地包含第一和第二锁存器，每个锁存器具有相应的多个不同的可能锁存值。 利用一个或多个语句，第一拨号实例与第一锁存器相关联，并且第二拨号实例与第二锁存器相关联。 因此，第一拨号实例的设置控制多个不同可能值中的哪一个加载到第一锁存器中，并且第二拨号实例的设置控制多个不同可能值中的哪一个加载到第二锁存器中。 通过语句，寄存器实例同时与第一和第二锁存器相关联，使得寄存器实例的设置控制加载在第一和第二锁存器中的锁存值。

公开(公告)号：US20050278683A1

公开(公告)日：2005-12-15

申请号：US10857461

申请日：2004-05-28

申请人： Wolfgang Roesner ,  Derek Williams

发明人： Wolfgang Roesner ,  Derek Williams

IPC分类号： G06F17/50

CPC分类号： G06F17/5022 ,  G06F17/505

摘要： In at least one hardware definition language (HDL) file, at least one design entity containing a functional portion of a digital system is specified. The design entity logically contains first and second latches each having a respective plurality of different possible latch values. With one or more statements, a first Dial instance is associated with the first latch and a second Dial instance is associated with the second latch. A setting of the first Dial instance thus controls which of the plurality of different possible values is loaded in the first latch, and a setting of the second Dial instance controls which of the plurality of different possible values is loaded in the second latch. With a statement, a Register instance is concurrently associated with both the first and the second latches, such that a setting of the Register instance controls the latch values loaded in both the first and second latches.

摘要翻译： 在至少一个硬件定义语言（HDL）文件中，指定包含数字系统的功能部分的至少一个设计实体。 设计实体逻辑地包含第一和第二锁存器，每个锁存器具有相应的多个不同的可能锁存值。 利用一个或多个语句，第一拨号实例与第一锁存器相关联，并且第二拨号实例与第二锁存器相关联。 因此，第一拨号实例的设置控制多个不同可能值中的哪一个加载到第一锁存器中，并且第二拨号实例的设置控制多个不同可能值中的哪一个加载到第二锁存器中。 通过语句，寄存器实例同时与第一和第二锁存器相关联，使得寄存器实例的设置控制加载在第一和第二锁存器中的锁存值。

公开(公告)号：US20060271743A1

公开(公告)日：2006-11-30

申请号：US11136652

申请日：2005-05-24

申请人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke ,  Derek Williams

发明人： Leo Clark ,  James Fields ,  Guy Guthrie ,  William Starke ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0831

摘要： Scrubbing logic in a local coherency domain issues a domain query request to at least one cache hierarchy in a remote coherency domain. The domain query request is a non-destructive probe of a coherency state associated with a target memory block by the at least one cache hierarchy. A coherency response to the domain query request is received. In response to the coherency response indicating that the target memory block is not cached in the remote coherency domain, a domain indication in the local coherency domain is updated to indicate that the target memory block is cached, if at all, only within the local coherency domain.

公开(公告)号：US20080040556A1

公开(公告)日：2008-02-14

申请号：US11835984

申请日：2007-08-08

申请人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Derek Williams

发明人： James Fields ,  Benjiman Goodman ,  Guy Guthrie ,  William Starke ,  Derek Williams

IPC分类号： G06F12/08

CPC分类号： G06F12/0817 ,  G06F12/0831 ,  G06F12/084

摘要： A cache coherent data processing system includes at least first and second coherency domains each including at least one processing unit. The first coherency domain includes a first cache memory and a second cache memory, and the second coherency domain includes a remote coherent cache memory. The first cache memory includes a cache controller, a data array including a data storage location for caching a memory block, and a cache directory. The cache directory includes a tag field for storing an address tag in association with the memory block and a coherency state field associated with the tag field and the data storage location. The coherency state field has a plurality of possible states including a state that indicates that the memory block is possibly shared with the second cache memory in the first coherency domain and cached only within the first coherency domain.

摘要翻译： 高速缓存一致数据处理系统至少包括第一和第二相关域，每个域包括至少一个处理单元。 第一相关域包括第一高速缓存存储器和第二高速缓冲存储器，并且第二相干域包括远程一致高速缓存存储器。 第一高速缓存存储器包括高速缓存控制器，包括用于高速缓存存储器块的数据存储位置的数据阵列和高速缓存目录。 缓存目录包括用于存储与存储器块相关联的地址标签的标签字段和与标签字段和数据存储位置相关联的一致性状态字段。 相关性状态字段具有多个可能的状态，包括指示存储器块可能与第一相关域中的第二高速缓冲存储器共享并且仅在第一相干域内缓存的状态。

公开(公告)号：US20060179253A1

公开(公告)日：2006-08-10

申请号：US11054841

申请日：2005-02-10

申请人： James Fields ,  Guy Guthrie ,  William Starke ,  Derek Williams

发明人： James Fields ,  Guy Guthrie ,  William Starke ,  Derek Williams

IPC分类号： G06F13/28

CPC分类号： G06F12/0831 ,  G06F12/0813 ,  G06F2212/1016 ,  G06F2212/1048

摘要： A data processing system includes a memory system, a plurality of masters that issue requests for access to memory blocks within the memory system, a plurality of snoopers that provide partial responses to requests by the masters, and response logic that generates combined responses for the requests in response to the partial responses provided by the plurality of snoopers. The plurality masters includes a winning master that issues a request for a particular memory block, and the plurality of snoopers includes a protecting snooper that, in response to receipt of the request, provides a partial response and protects a transfer of coherency ownership of the particular memory block to the winning master until expiration of a protection window extension following receipt from the response logic of a combined response for the request.

摘要翻译： 数据处理系统包括存储器系统，发出对存储器系统内的存储器块的访问请求的多个主器件，提供对由主器件发出的请求的部分响应的多个监视器以及产生针对请求的组合响应的响应逻辑 响应于由多个窥探者提供的部分响应。 多个主人包括发出对特定存储块的请求的获胜主，并且多个窥探者包括保护窥探者，其响应于该请求的接收而提供部分响应并保护特定存储块的一致性所有权的转移 记忆块到获胜主机，直到从请求的组合响应的响应逻辑接收到保护窗口扩展之后到期。

公开(公告)号：US20070088926A1

公开(公告)日：2007-04-19

申请号：US11250022

申请日：2005-10-13

申请人： James Fields ,  Guy Guthrie ,  John Hollaway ,  Derek Williams

发明人： James Fields ,  Guy Guthrie ,  John Hollaway ,  Derek Williams

IPC分类号： G06F12/14

CPC分类号： G06F12/0831 ,  G06F12/0815 ,  G06F12/0824

摘要： A data processing system includes a plurality of requestors and a memory controller for a system memory. In response to receiving from the requestor a read-type request targeting a memory block in the system memory, the memory controller protects the memory block from modification, and in response to an indication that the memory controller is responsible for servicing the read-type request, the memory controller transmits the memory block to the requestor. Prior to receipt of the memory block by the requestor, the memory controller ends protection of the memory block from modification, and the requestor begins protection of the memory block from modification. In response to receipt of the memory block, the requestor ends its protection of the memory block from modification.

摘要翻译： 数据处理系统包括多个请求者和用于系统存储器的存储器控​​制器。 响应于从请求者接收到针对系统存储器中的存储器块的读取型请求，存储器控制器保护存储器块免受修改，并且响应于存储器控制器负责维护读取类型请求的指示 存储器控制器将该存储器块发送给请求者。 在请求者接收到存储器块之前，存储器控制器结束对存储器块的保护而不被修改，并且请求者开始保护存储器块免受修改。 响应于存储器块的接收，请求者结束其对存储器块的保护以免修改。