公开(公告)号：US20190251903A1

公开(公告)日：2019-08-15

申请号：US16394113

申请日：2019-04-25

Applicant: Japan Display Inc.

Inventor： Tetsuo MORITA ,  Hiroyuki Kimura ,  Makoto Shibusawa ,  Hiroshi Tabatake ,  Yasuhiro Ogawa

IPC: G09G3/3233 ,  G02F1/1345 ,  H01L27/12 ,  H01L27/32 ,  H01L29/786

CPC classification number: G09G3/3233 ,  G02F1/13452 ,  G02F1/13454 ,  G02F1/13624 ,  G02F1/136286 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0256 ,  G09G2320/0238 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/1255 ,  H01L27/3262 ,  H01L27/3272 ,  H01L29/7869

Abstract: Disclosed is a display device including: a driving transistor, a first switching transistor, and a pixel transistor each having a gate and a pair of terminals; a storage capacitor having a pair of terminals; and a light-emitting element having an input terminal and an output terminal. One terminal of the driving transistor is electrically connected to one terminal of the pixel transistor. The other terminal of the driving transistor is electrically connected to one terminal of the first switching transistor and the input terminal of the light-emitting element. The other terminal of the first switching transistor is electrically connected to the gate of the driving transistor and one terminal of the capacitor. The one terminal of the capacitor overlaps with an active region of the driving transistor.

公开(公告)号：US20180374415A1

公开(公告)日：2018-12-27

申请号：US15633960

申请日：2017-06-27

Applicant: Japan Display Inc.

Inventor： Tetsuo MORITA ,  Hiroyuki KIMURA ,  Makoto SHIBUSAWA ,  Hiroshi TABATAKE ,  Yasuhiro OGAWA

IPC: G09G3/3225 ,  H01L27/32

CPC classification number: G09G3/3225 ,  G09G3/3233 ,  G09G3/3266 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0251 ,  G09G2310/0262 ,  G09G2310/0291 ,  G09G2310/08 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/1255 ,  H01L27/3262 ,  H01L29/78672 ,  H01L29/7869

Abstract: A display device includes a pixel region having a plurality of pixel and a driver circuit outside the pixel region. The pixels have a driving transistor and a switching transistor having a gate and a pair of terminals, a light-emitting element having an input terminal, and a storage capacitor having a pair of terminals. One terminal of the switching transistor is electrically connected to the gate of the driving transistor and one terminal of the storage capacitor. One terminal of the driving transistor is electrically connected to the other terminal of the storage capacitor and the input terminal. The driver circuit includes first and second transistors having a gate and a pair of terminal. The other terminal of the switching transistor is electrically connected to one terminal of the first transistor and one terminal of the second transistor. The second transistor has a channel region including an oxide semiconductor.

公开(公告)号：US20180061317A1

公开(公告)日：2018-03-01

申请号：US15670241

申请日：2017-08-07

Applicant: Japan Display Inc.

Inventor： Tetsuo MORITA ,  Hiroyuki KIMURA ,  Makoto SHIBUSAWA ,  Hiroshi TABATAKE ,  Yasuhiro OGAWA

IPC: G09G3/3233 ,  H01L27/12 ,  H01L27/32 ,  H01L29/786 ,  G02F1/1362 ,  G02F1/1345

CPC classification number: G09G3/3233 ,  G02F1/13452 ,  G02F1/13454 ,  G02F1/13624 ,  G02F1/136286 ,  G09G2300/0819 ,  G09G2300/0842 ,  G09G2300/0861 ,  G09G2310/0256 ,  G09G2320/0238 ,  H01L27/1225 ,  H01L27/1251 ,  H01L27/1255 ,  H01L27/3262 ,  H01L27/3272 ,  H01L29/7869

Abstract: Disclosed is a display device including: a driving transistor, a first switching transistor, and a pixel transistor each having a gate and a pair of terminals; a storage capacitor having a pair of terminals; and a light-emitting element having an input terminal and an output terminal. One terminal of the driving transistor is electrically connected to one terminal of the pixel transistor. The other terminal of the driving transistor is electrically connected to one terminal of the first switching transistor and the input terminal of the light-emitting element. The other terminal of the first switching transistor is electrically connected to the gate of the driving transistor and one terminal of the capacitor. The one terminal of the capacitor overlaps with an active region of the driving transistor.

公开(公告)号：US20180019291A1

公开(公告)日：2018-01-18

申请号：US15496043

申请日：2017-04-25

Applicant: Japan Display Inc.

Inventor： Tetsuo MORITA ,  Hiroyuki KIMURA ,  Makoto SHIBUSAWA ,  Hiroshi TABATAKE ,  Yasuhiro OGAWA

IPC: H01L27/32 ,  H01L29/786

CPC classification number: H01L27/3262 ,  H01L27/3265 ,  H01L29/78675 ,  H01L29/7869 ,  H01L29/78696

Abstract: Provided is a display device including a plurality of pixels at least one of which has a first transistor and a light-emitting element. The first transistor includes a gate electrode, a gate insulating film over the gate electrode, an oxide semiconductor film over the gate insulating film, and a first terminal and a second terminal electrically connected to the semiconductor film. The second terminal is electrically connected to the light-emitting element. A region in which the first terminal overlaps with the gate electrode can be smaller than a region in which the second terminal overlaps with the gate electrode.

公开(公告)号：US20240334768A1

公开(公告)日：2024-10-03

申请号：US18597964

申请日：2024-03-07

Applicant: Japan Display Inc.

Inventor： Hideyuki TAKAHASHI ,  Hiroyuki KIMURA ,  Hiroshi TABATAKE ,  Tetsuo MORITA

IPC: H10K59/131

CPC classification number: H10K59/131

Abstract: According to one embodiment, a display device includes a display area which includes a plurality of subpixels, a plurality of lower electrodes provided in the subpixels, respectively, a plurality of organic layers which cover the lower electrodes, respectively, and emit light based on applied voltage, and a common electrode which covers the organic layers and overlaps the display area. Further, the common electrode has a slit in which at least an end reaches an outer edge of the common electrode.

公开(公告)号：US20240331627A1

公开(公告)日：2024-10-03

申请号：US18619597

申请日：2024-03-28

Applicant: Japan Display Inc.

Inventor： Yukio TANAKA ,  Tetsuo MORITA ,  Yutaka UMEDA

IPC: G09G3/3225

CPC classification number: G09G3/3225 ,  G09G2300/0842 ,  G09G2310/08 ,  G09G2320/0247 ,  G09G2360/16

Abstract: An EL display device is controlled to emit light so as to effectively reduce a flicker even when low-frequency driving is used at any frequency. In a light emission control method of the EL display device including a plurality of regularly arranged light emitting elements, one or more non-light emission periods, in which the light emitting element does not emit, are inserted in one emission cycle of the light emitting element. In a luminance change of the light emitting element at the emission cycle of T≡2π/ω, l is a largest natural number with respect to a threshold frequency ωth/2π0 to satisfy lω≤ωth, the following holds:






∑

n
=
1

l




❘
"\[LeftBracketingBar]"


c
n


❘
"\[RightBracketingBar]"


2


≦


1
2

⁢


∑

n
=
1

∞




❘
"\[LeftBracketingBar]"


c
n


❘
"\[RightBracketingBar]"


2







where n is an integer and cn is a complex Fourier coefficient of luminance L(t) of the light emitting element in a section 0≤t

公开(公告)号：US20240194140A1

公开(公告)日：2024-06-13

申请号：US18524291

申请日：2023-11-30

Applicant: Japan Display Inc.

Inventor： Tetsuo MORITA

IPC: G09G3/3233

CPC classification number: G09G3/3233 ,  G09G2300/0426 ,  G09G2300/0819 ,  G09G2300/0861 ,  G09G2330/021 ,  G09G2330/045

Abstract: A display device includes a first transistor controlled using a second control signal obtained by shifting a first control signal and electrically connected a first node, a second transistor electrically connected between the first node and a second node, a third transistor controlled using the first control signal to which a third control signal has been shifted, and electrically connected between the second node and a gate electrode of the second transistor, and a fourth transistor electrically connected to the second node is controlled to supply a reset voltage to the second node and the gate electrode of the second transistor using the third control signal.

公开(公告)号：US20240087515A1

公开(公告)日：2024-03-14

申请号：US18516161

申请日：2023-11-21

Applicant: Japan Display Inc.

Inventor： Hiroshi TABATAKE ,  Tetsuo MORITA

IPC: G09G3/3225 ,  H10K59/131

CPC classification number: G09G3/3225 ,  H10K59/1315 ,  G09G3/3258 ,  G09G2310/061 ,  G09G2330/02

Abstract: According to one embodiment, a display device includes a base, a plurality of pixels, a power supply line and a power supply line drive circuit. The pixels each include a pixel circuit, a display element including a lower electrode, an upper electrode and an organic layer including a light-emitting layer. The upper electrode is connected to the power supply line that provides a predetermined potential to the upper electrode. The power supply line drive circuit supplies, to the power supply line, a first potential to the upper electrode during a light-emitting period and supplies, to the power supply line, a second potential to the upper electrode during a non-light-emitting period.

公开(公告)号：US20230111936A1

公开(公告)日：2023-04-13

申请号：US18080806

申请日：2022-12-14

Applicant: Japan Display Inc.

Inventor： Tetsuo MORITA ,  Yasuhiro OGAWA

IPC: G09G3/32 ,  G09G3/20 ,  H01L25/075

Abstract: According to one embodiment, a display device includes a display region where pixels are arranged. Each of the pixels includes a pixel electrode, a light emitting element, a drive transistor, a first capacitance electrode layer opposed to the pixel electrode and held at a constant potential, and an insulating layer forming an auxiliary capacitance together with the pixel electrode and the first capacitance electrode layer. A value of the auxiliary capacitance of the first pixel, of the values of the auxiliary capacitance of the pixels is the largest.

公开(公告)号：US20220310003A1

公开(公告)日：2022-09-29

申请号：US17696941

申请日：2022-03-17

Applicant: Japan Display Inc.

Inventor： Kenji HARADA ,  Tetsuo MORITA

IPC: G09G3/3208

Abstract: A bootstrap circuit includes a first transistor including a gate electrode, a first and a second electrodes, a capacitor connected between the gate electrode and the second electrode, and a second transistor connected to the gate electrode. In a first period, the second transistor is turned on and the gate electrode is supplied with a first analog voltage, the first transistor is turned on, and the second electrode is supplied with a precharge voltage smaller than the first analog voltage from the first electrode. In a second period, the second transistor is turned off, the first electrode is supplied with a second analog voltage, the capacitor supplies a third analog voltage to the gate electrode in response to the first analog voltage and the second analog voltage, and the second electrode is supplied with the second analog voltage from the first electrode.