公开(公告)号：US06649461B1

公开(公告)日：2003-11-18

申请号：US10132356

申请日：2002-04-25

申请人： Tommy Mau Lam Lai ,  Weining Li ,  Yung Tao Lin

发明人： Tommy Mau Lam Lai ,  Weining Li ,  Yung Tao Lin

IPC分类号： H01L218238

CPC分类号： H01L21/76224 ,  H01L21/823814 ,  H01L21/823878

摘要： A new angle implant is provided that reduces or eliminates the effects of narrow channel impurity diffusion to surrounding regions of insulation. The invention provides for angle implantation of p-type impurities into corners of STI regions that are adjacent to NMOS devices and angle implantation of n-type impurities into corners of STI regions that are adjacent to PMOS devices.

摘要翻译： 提供了一种新的角度注入，其减少或消除了窄通道杂质扩散对周围绝缘区域的影响。 本发明提供了将p型杂质角度注入到与NMOS器件相邻的STI区域的角部，并且将n型杂质角度注入到与PMOS器件相邻的STI区域的拐角中。

公开(公告)号：US06177304B1

公开(公告)日：2001-01-23

申请号：US09298933

申请日：1999-04-26

申请人： Weining Li ,  Yung-Tao Lin ,  Mau Lam Lai ,  Tin Tin Wee

发明人： Weining Li ,  Yung-Tao Lin ,  Mau Lam Lai ,  Tin Tin Wee

IPC分类号： H01L218238

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823475 ,  H01L21/823481

摘要： A method for integrating salicide and self-aligned contact processes in the fabrication of logic circuits with embedded memory is described. Isolation areas are formed on a semiconductor substrate surrounding and electrically isolating device areas. Gate electrodes and associated source and drain regions are formed on and in the semiconductor substrate wherein the gate electrodes have silicon nitride sidewall spacers. A metal silicide layer is formed on the top surface of the gate electrodes and on the top surface of the semiconductor substrate overlying the source and drain regions associated with the gate electrodes using a salicide process. A poly-cap layer is deposited overlying the substrate. The poly-cap layer is selectively removed overlying one of the salicided source and drain regions where a self-aligned contact is to be formed, and overlying another of the salicided source and drain regions and a portion of its associated salicided gate electrode where a butted contact is to be formed. An insulating layer is deposited over the surface of the semiconductor substrate. The insulating layer is etched through to form simultaneously the planned self-aligned contact opening and the planned butted contact opening. The self-aligned contact opening and the butted contact opening are filled with a conducting layer to complete fabrication of the integrated circuit device.

摘要翻译： 描述了在具有嵌入式存储器的逻辑电路的制造中整合自杀化和自对准接触过程的方法。 隔离区域形成在围绕并电隔离器件区域的半导体衬底上。 栅极电极和相关的源极和漏极区域形成在半导体衬底上和栅极中具有氮化硅侧壁间隔物。 使用自对准硅化物工艺在栅电极的顶表面和半导体衬底的顶表面上形成金属硅化物层，覆盖与栅电极相关的源极和漏极区域。 多层覆盖层沉积在衬底上。 选择性地去除聚盖层，覆盖其中要形成自对准接触的水银源区和漏区之一，并且覆盖另一个水银源和漏区及其相关联的盐化栅极的一部分，其中对接 接触将被形成。 绝缘层沉积在半导体衬底的表面上。 绝缘层被蚀刻通过以形成计划的自对准接触开口和计划的对接接触开口。 自对准的接触开口和对接的接触开口填充有导电层，以完成集成电路器件的制造。

公开(公告)号：US20050101102A1

公开(公告)日：2005-05-12

申请号：US10703289

申请日：2003-11-06

申请人： Tze Ho Chan ,  Weining Li ,  Elgin Quek ,  Jia Zheng ,  Pradeep Ramachandramurthy Yelehanka ,  Tommy Lai

发明人： Tze Ho Chan ,  Weining Li ,  Elgin Quek ,  Jia Zheng ,  Pradeep Ramachandramurthy Yelehanka ,  Tommy Lai

IPC分类号： H01L21/336 ,  H01L21/762 ,  H01L21/8247 ,  H01L27/115 ,  H01L21/76

CPC分类号： H01L27/11521 ,  H01L21/76237 ,  H01L27/115 ,  H01L29/66825

摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming two trenches in the semiconductor substrate to define an active region therebetween. An implanted source region is formed in one of the trenches on one side of the active region. An implanted drain region is formed in the other trench on the other side of the active region. Shallow trench isolations are then formed in the trenches. One or more gates are formed over the active region, and contacts to the implanted source region and the implanted drain region are formed.

摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在半导体衬底中形成两个沟槽以在其间限定有源区。 植入的源极区域形成在有源区域的一侧的沟槽中的一个中。 在有源区的另一侧的另一个沟槽中形成注入的漏极区。 然后在沟槽中形成浅沟槽隔离。 在有源区域上形成一个或多个栅极，并且形成与注入源极区域和注入的漏极区域的接触。

公开(公告)号：US20050085056A1

公开(公告)日：2005-04-21

申请号：US10689923

申请日：2003-10-17

申请人： Tommy Lai ,  Pradeep Ramachandramurthy Yelehanka ,  Jia Zheng ,  Weining Li

发明人： Tommy Lai ,  Pradeep Ramachandramurthy Yelehanka ,  Jia Zheng ,  Weining Li

IPC分类号： H01L21/3115 ,  H01L21/314 ,  H01L21/8239 ,  H01L21/8247 ,  H01L21/425 ,  H01L21/336 ,  H01L21/31 ,  H01L21/469

CPC分类号： H01L21/022 ,  H01L21/02164 ,  H01L21/0217 ,  H01L21/31155 ,  H01L21/3144 ,  H01L27/1052 ,  H01L27/11546

摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming at least one oxide-nitride-oxide dielectric layer above the semiconductor substrate. At least one implantation is formed into at least one area of the semiconductor substrate beneath the oxide-nitride-oxide dielectric layer subsequent to the formation of the oxide-nitride-oxide dielectric layer.

摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在半导体衬底上形成至少一个氧化物 - 氮化物 - 氧化物电介质层。 在形成氧化物 - 氮化物 - 氧化物电介质层之后，至少一个注入形成在氧化物 - 氮化物 - 氧化物介电层下方的半导体衬底的至少一个区域中。

公开(公告)号：US08817132B1

公开(公告)日：2014-08-26

申请号：US12690302

申请日：2010-01-20

申请人： Weining Li

发明人： Weining Li

IPC分类号： H04N9/64

CPC分类号： H04N5/367 ,  H04N5/3765

摘要： A method for synchronizing a first circuit to an electro-optical sensor is disclosed. The method generally includes steps (A) to (D). Step (A) may generate with the first circuit a configuration signal that conveys a request to capture at least one frame of a plurality of periodic frames. Step (B) may receive the periodic frames at a second circuit from the electro-optical sensor. Step (C) may discard a first frame of the periodic frames where the first frame precedes the request. Step (D) may store a plurality of active pixels in a second frame of the periodic frames in a memory where the second frame follows the request. The second circuit is generally a hardware implementation.

摘要翻译： 公开了一种使第一电路与电光传感器同步的方法。 该方法通常包括步骤（A）至（D）。 步骤（A）可以利用第一电​​路产生传送请求以捕获多个周期性帧的至少一个帧的配置信号。 步骤（B）可以在来自电光传感器的第二电路处接收周期性帧。 步骤（C）可以丢弃其中第一帧在请求之前的周期性帧的第一帧。 步骤（D）可将多个有源像素存储在周期性帧的第二帧中，其中第二帧遵循该请求。 第二电路通常是硬件实现。

公开(公告)号：US20050098794A1

公开(公告)日：2005-05-12

申请号：US11009772

申请日：2004-12-11

申请人： Elgin Quek ,  Pradeep Ramachandramurthy Yelehanka ,  Jia Zheng ,  Tommy Lai ,  Weining Li

发明人： Elgin Quek ,  Pradeep Ramachandramurthy Yelehanka ,  Jia Zheng ,  Tommy Lai ,  Weining Li

IPC分类号： H01L21/332 ,  H01L21/8244 ,  H01L27/11 ,  H01L29/423

CPC分类号： H01L29/66393 ,  H01L27/11

摘要： An integrated circuit structure includes a semiconductor substrate and a thyristor formed thereon. The thyristor has at least four layers, with three P-N junctions therebetween. At least two of the layers are formed horizontally and at least two of the layers are formed vertically. A gate is formed adjacent at least one of the vertically formed layers. An access transistor is formed on the semiconductor substrate, and an interconnect is formed between the thyristor and the access transistor.

摘要翻译： 集成电路结构包括形成在其上的半导体衬底和晶闸管。 晶闸管具有至少四层，其间具有三个P-N结。 至少两层是水平形成的，并且至少两层是垂直形成的。 在至少一个垂直形成的层之间形成栅极。 在半导体衬底上形成存取晶体管，并且在晶闸管和存取晶体管之间形成互连。

公开(公告)号：US20050079674A1

公开(公告)日：2005-04-14

申请号：US10683052

申请日：2003-10-09

申请人： Zia Zheng ,  Pradeep Ramachandramurthy Yelehanka ,  Weining Li

发明人： Zia Zheng ,  Pradeep Ramachandramurthy Yelehanka ,  Weining Li

IPC分类号： H01L21/336 ,  H01L21/8246 ,  H01L27/105 ,  H01L27/115

CPC分类号： H01L27/11568 ,  H01L27/105 ,  H01L27/115 ,  H01L27/11573

摘要： A method for manufacturing an integrated circuit structure includes providing a semiconductor substrate and forming a gate dielectric layer over the semiconductor substrate. The gate dielectric layer is formed in a plurality of thicknesses in a plurality of devices regions over the semiconductor substrate. A second dielectric layer is formed over at least one of the devices regions. A third dielectric layer is formed over at least a portion of the second dielectric layer. Ion traps are then selectively implanted in portions of the second dielectric layer.

摘要翻译： 一种用于制造集成电路结构的方法包括提供半导体衬底并在半导体衬底上形成栅介质层。 栅极电介质层在半导体衬底上的多个器件区域中形成多个厚度。 在至少一个器件区域上形成第二介电层。 在第二电介质层的至少一部分上形成第三电介质层。 然后在第二介电层的部分中选择性地注入离子阱。

公开(公告)号：US06376298B1

公开(公告)日：2002-04-23

申请号：US09494636

申请日：2000-01-31

申请人： Weining Li ,  Yung-Tao Lin

发明人： Weining Li ,  Yung-Tao Lin

IPC分类号： H01L218234

CPC分类号： H01L21/76897 ,  H01L21/823481

摘要： A method for integrating salicide and self-aligned contact processes in the fabrication of integrated circuits by using a poly cap mask and a special layout technique is described. A pair of gate electrodes and associated source and drain regions are formed overlying a semiconductor substrate wherein nitride spacers are formed on sidewalls of the gate electrodes. A poly-cap layer is deposited overlying the gate electrodes and source and drain regions. The poly-cap layer is selectively removed overlying one of the source and drain regions between the gate electrode pair where a self-aligned contact is to be formed and removed over one of the gate electrode pair. An insulating layer is deposited over the surface of the semiconductor substrate. The planned self-aligned contact opening is made through the insulating layer to the source/drain region to be contacted wherein the contact opening partially overlies the poly-cap layer over the adjacent gate electrode of the pair. The self-aligned contact opening is filled with a conducting layer to complete fabrication of the integrated circuit device.

摘要翻译： 描述了通过使用聚盖掩模和特殊布局技术在集成电路的制造中整合自对准和自对准接触工艺的方法。 一对栅电极和相关的源极和漏极区域形成在半导体衬底上，其中在栅电极的侧壁上形成氮化物间隔物。 覆盖栅电极和源极和漏极区的多晶硅层被沉积。 选择性地去除聚盖层，覆盖栅极电极对之间的源极和漏极区域之一，其中将形成自对准接触并在栅极电极对中的一个上去除。 绝缘层沉积在半导体衬底的表面上。 计划的自对准接触开口通过绝缘层到待接触的源极/漏极区域，其中接触开口部分地覆盖在该对的相邻栅电极上的多晶硅层。 自对准接触开口填充有导电层以完成集成电路器件的制造。