公开(公告)号：US06649461B1

公开(公告)日：2003-11-18

申请号：US10132356

申请日：2002-04-25

申请人： Tommy Mau Lam Lai ,  Weining Li ,  Yung Tao Lin

发明人： Tommy Mau Lam Lai ,  Weining Li ,  Yung Tao Lin

IPC分类号： H01L218238

CPC分类号： H01L21/76224 ,  H01L21/823814 ,  H01L21/823878

摘要： A new angle implant is provided that reduces or eliminates the effects of narrow channel impurity diffusion to surrounding regions of insulation. The invention provides for angle implantation of p-type impurities into corners of STI regions that are adjacent to NMOS devices and angle implantation of n-type impurities into corners of STI regions that are adjacent to PMOS devices.

摘要翻译： 提供了一种新的角度注入，其减少或消除了窄通道杂质扩散对周围绝缘区域的影响。 本发明提供了将p型杂质角度注入到与NMOS器件相邻的STI区域的角部，并且将n型杂质角度注入到与PMOS器件相邻的STI区域的拐角中。

公开(公告)号：US06569699B1

公开(公告)日：2003-05-27

申请号：US09495347

申请日：2000-02-01

申请人： Yung-Tao Lin ,  Sik On Kong

发明人： Yung-Tao Lin ,  Sik On Kong

IPC分类号： H01L2100

CPC分类号： G02F1/136277 ,  G02F1/133553 ,  G02F2001/133357

摘要： A method of fabricating an LCD-on-silicon pixel device including the following steps. A substrate having an upper layer of silicon is provided. A via is formed in the silicon layer. An opaque conducting layer is deposited over the silicon layer, filling the via. The opaque conducting layer is planarized a reflective layer is deposited over the opaque conducting layer. Alternatively, the via may be formed by a deposition and etch back process with one metal. An opaque conducting layer is then deposited and planarized before deposition of the reflective layer. An LCD-on-silicon pixel device, comprises a substrate having an upper silicon layer. The upper silicon layer has a plug therein comprised of an opaque conducting material. Over the upper silicon layer and the opaque conducting plug is a planar opaque conducting layer and a planar reflective layer is over the planar opaque conducting layer.

摘要翻译： 一种制造包括以下步骤的硅上硅像素装置的方法。 提供了具有上层硅的衬底。 在硅层中形成通孔。 在硅层上沉积不透明导电层，填充通孔。 不透明导电层被平坦化，反射层沉积在不透明导电层上。 或者，可以通过用一种金属的沉积和回蚀工艺形成通孔。 然后在沉积反射层之前沉积不平坦的导电层并进行平坦化。 一种硅上像素元件，包括具有上硅层的衬底。 上硅层具有由不透明导电材料构成的塞子。 在上硅层和不透明导电插塞之上是平面不透明导电层，并且平面反射层在平面不透明导电层之上。

公开(公告)号：US06284603B1

公开(公告)日：2001-09-04

申请号：US09614555

申请日：2000-07-12

申请人： Chan Tze Ho Simon ,  Tyrone Philip Stodart ,  Sung Rae Kim ,  Yung-Tao Lin

发明人： Chan Tze Ho Simon ,  Tyrone Philip Stodart ,  Sung Rae Kim ,  Yung-Tao Lin

IPC分类号： H01L218247

CPC分类号： H01L29/66825 ,  H01L21/26586 ,  H01L29/7883 ,  Y10S438/983

摘要： A new method of fabricating a Flash EEPROM memory cell is achieved. Ions are optionally implanted into said semiconductor substrate to form threshold enhancement regions of the same type as the semiconductor substrate. A tunneling oxide is formed. A first conductive layer is deposited. An interpoly oxide layer is deposited. A second conductive layer is deposited. The second conductive layer, the interpoly oxide layer, the first conductive layer, and the tunneling oxide layer are patterned to form control gates and floating gates. Ions are implanted to form drain junctions. A mask protects the planned source junctions. The drain junctions are opposite type to the semiconductor substrate. Ions are implanted to form source junctions. A mask protects the drain junctions. The source junctions are opposite type to the semiconductor substrate. Ions are implanted to form channel stop junctions to complete the Flash EEPROM memory cells. The ion implantation is performed at a non-perpendicular angle with respect to the substrate. The channel stop junctions contain the source junctions. The channel stop junctions are opposite type to the semiconductor substrate. A mask protects the drain junctions.

摘要翻译： 实现了制造闪存EEPROM存储单元的新方法。 任选地将离子注入到所述半导体衬底中以形成与半导体衬底相同类型的阈值增强区域。 形成隧道氧化物。 沉积第一导电层。 沉积了多晶氧化层。 沉积第二导电层。 将第二导电层，多晶硅氧化物层，第一导电层和隧道氧化物层图案化以形成控制栅极和浮栅。 植入离子以形成排水路口。 面罩保护计划的源路口。 漏极结与半导体衬底相反。 植入离子以形成源结。 掩模保护排水路口。 源极结与半导体衬底相反。 离子被植入以形成通道停止接头以完成闪存EEPROM存储单元。 以相对于衬底的非垂直角度执行离子注入。 通道停止点包含源路口。 通道停止接头与半导体衬底相反。 面罩保护排水路口。

公开(公告)号：US06180430B2

公开(公告)日：2001-01-30

申请号：US09458726

申请日：1999-12-13

申请人： Sik On Kong ,  Dai Feng ,  Yung-Tao Lin ,  Robert Chin Fu Tsai

发明人： Sik On Kong ,  Dai Feng ,  Yung-Tao Lin ,  Robert Chin Fu Tsai

IPC分类号： H01L2100

CPC分类号： G02F1/133512 ,  G02F1/136

摘要： A method of fabricating an LCD-on-silicon device, comprising the following steps. A semiconductor structure having a control transistor formed therein is provided. The control transistor having a source and a drain. An interlevel dielectric (ILD) layer over the semiconductor structure is provided. Source/drain (S/D) plugs contacting the source and drain through contact openings in said ILD layer are provided. M1 lines are formed over the ILD layer and connected to at least the S/D plugs. An M1 intermetal dielectric (IMD) layer is deposited and patterned over the M1 lines to form M1 contact openings exposing at least some of the M1 metal lines. M1 metal plugs are formed within the M1 contact openings and M2 metal islands connected to, and integral with, at least the M1 metal plugs. The M2 metal islands having exposed side walls. Sidewall spacers are formed on the exposed M2 metal islands side walls. A second M2 metallization layer is deposited and patterned over the M2 metal islands to form a shielding layer adjacent to and contiguous with the sidewall spacers. The M2 metal islands, sidewall spacers, and shielding layer form a light shielding layer. At least one additional dielectric and conductive layer is formed over the light shielding layer and the M1 intermetal dielectric (IMD) layer. LCD pixels are then formed thereover.

摘要翻译： 一种制造硅 - 硅器件的方法，包括以下步骤。 提供了其中形成有控制晶体管的半导体结构。 控制晶体管具有源极和漏极。 提供半导体结构上的层间电介质（ILD）层。 提供了通过所述ILD层中的接触开口接触源极和漏极的源极/漏极（S / D）插塞。 M1线形成在ILD层上并且连接到至少S / D插头。 在M1线上沉积并图案化M1金属间电介质（IMD）层，以形成暴露至少一些M1金属线的M1接触开口。 M1金属插塞形成在M1接触开口和M2金属岛之间，M2金属岛连接到至少M1金属插头并与其成一体。 M2金属岛具有暴露的侧壁。 在暴露的M2金属岛侧壁上形成侧壁间隔物。 在M2金属岛上沉积和图案化第二M2金属化层以形成与侧壁间隔物相邻并邻接的屏蔽层。 M2金属岛，侧壁间隔物和屏蔽层形成遮光层。 在遮光层和M1金属间电介质（IMD）层上形成至少一个附加的电介质层和导电层。 然后在其上形成LCD像素。

公开(公告)号：US06177304B1

公开(公告)日：2001-01-23

申请号：US09298933

申请日：1999-04-26

申请人： Weining Li ,  Yung-Tao Lin ,  Mau Lam Lai ,  Tin Tin Wee

发明人： Weining Li ,  Yung-Tao Lin ,  Mau Lam Lai ,  Tin Tin Wee

IPC分类号： H01L218238

CPC分类号： H01L21/76897 ,  H01L21/76895 ,  H01L21/823475 ,  H01L21/823481

摘要： A method for integrating salicide and self-aligned contact processes in the fabrication of logic circuits with embedded memory is described. Isolation areas are formed on a semiconductor substrate surrounding and electrically isolating device areas. Gate electrodes and associated source and drain regions are formed on and in the semiconductor substrate wherein the gate electrodes have silicon nitride sidewall spacers. A metal silicide layer is formed on the top surface of the gate electrodes and on the top surface of the semiconductor substrate overlying the source and drain regions associated with the gate electrodes using a salicide process. A poly-cap layer is deposited overlying the substrate. The poly-cap layer is selectively removed overlying one of the salicided source and drain regions where a self-aligned contact is to be formed, and overlying another of the salicided source and drain regions and a portion of its associated salicided gate electrode where a butted contact is to be formed. An insulating layer is deposited over the surface of the semiconductor substrate. The insulating layer is etched through to form simultaneously the planned self-aligned contact opening and the planned butted contact opening. The self-aligned contact opening and the butted contact opening are filled with a conducting layer to complete fabrication of the integrated circuit device.

摘要翻译： 描述了在具有嵌入式存储器的逻辑电路的制造中整合自杀化和自对准接触过程的方法。 隔离区域形成在围绕并电隔离器件区域的半导体衬底上。 栅极电极和相关的源极和漏极区域形成在半导体衬底上和栅极中具有氮化硅侧壁间隔物。 使用自对准硅化物工艺在栅电极的顶表面和半导体衬底的顶表面上形成金属硅化物层，覆盖与栅电极相关的源极和漏极区域。 多层覆盖层沉积在衬底上。 选择性地去除聚盖层，覆盖其中要形成自对准接触的水银源区和漏区之一，并且覆盖另一个水银源和漏区及其相关联的盐化栅极的一部分，其中对接 接触将被形成。 绝缘层沉积在半导体衬底的表面上。 绝缘层被蚀刻通过以形成计划的自对准接触开口和计划的对接接触开口。 自对准的接触开口和对接的接触开口填充有导电层，以完成集成电路器件的制造。

公开(公告)号：US5963780A

公开(公告)日：1999-10-05

申请号：US899739

申请日：1997-07-24

申请人： Zhi-Min Ling ,  Yung-Tao Lin ,  Ying Shiau

发明人： Zhi-Min Ling ,  Yung-Tao Lin ,  Ying Shiau

IPC分类号： H01L23/544 ,  H01L21/66 ,  G01R31/26

CPC分类号： H01L22/34 ,  H01L2924/0002

摘要： An apparatus and method for detecting defect sizes in polysilicon and source-drain semiconductor devices and methods for making the same. Implemented is a double bridge test structure that includes a resistor path of first semiconductor material, such as doped silicon comprising a plurality of strip segments and with interconnection segments. A plurality of strips of second semiconductor material having a substantially lower resistivity are connected to form parallel circuit interconnections with the corresponding strip segments. The test structure is formed by masking techniques wherein a prescribed mask region enables portions of the silicon resistor or deposited polysilicon to be selectively silicided to form silicide and polycide, respectively. One embodiment for testing for defects in a polysilicon layer uses polycide as the low-resistivity strips, enabling the testing of open and short-circuit defects. A second embodiment selectively silicides exposed portions of a source-drain resistor, thereby enabling testing for defects in a source-drain layer of a metal oxide semiconductor. Defect sizes are determined by comparing the measured resistance values with predetermined width and spacings of the strips.

摘要翻译： 用于检测多晶硅和源极 - 漏极半导体器件中的缺陷尺寸的装置和方法及其制造方法。 实现的是双桥测试结构，其包括第一半导体材料的电阻器路径，例如包括多个条带段和互连段的掺杂硅。 连接具有基本上较低电阻率的多个第二半导体材料带，以形成与相应条带段的并联电路互连。 测试结构通过掩模技术形成，其中规定的掩模区域使得硅电阻器或沉积的多晶硅的部分分别被选择性地硅化以形成硅化物和多硅化物。 用于测试多晶硅层中的缺陷的一个实施例使用聚硅氧烷作为低电阻率带，能够测试开路和短路缺陷。 第二实施例选择性地硅化源极 - 漏极电阻器的暴露部分，从而能够测试金属氧化物半导体的源极 - 漏极层中的缺陷。 通过将测得的电阻值与条的预定宽度和间距进行比较来确定缺陷尺寸。

公开(公告)号：US5917332A

公开(公告)日：1999-06-29

申请号：US647408

申请日：1996-05-09

申请人： Ming Chun Chen ,  Yung-Tao Lin

发明人： Ming Chun Chen ,  Yung-Tao Lin

IPC分类号： G01R31/311 ,  G01R31/265 ,  G06K9/74

CPC分类号： G01R31/311

摘要： Defect scanner sensitivity and accuracy are improved for light scattering defect scanners and pattern matching defect scanners by calibrating the defect scanners to each die on a wafer using preset marks on the corresponding die. The marks have a predetermined size based on the sensitivity of the defect scanners and a predetermined position relative to the circuit pattern on the corresponding die. Alignment of the defect scanners to a specific die provides improvement in coordinate accuracy over alignment with respect to an entire wafer. A layout mapping defect filtering system collects defect scan data and determines the interaction between the detected defects and a circuit layout. The layout mapping defect filtering system provides automatic identification in real time of killer defects that cause failure of the completed integrated circuit, and classifies and analyzes defects to identify potential killer defects within specified defect classes to identify defective die. The system provides accurate yield estimation to determine whether a produced wafer should be scrapped, and also provides accumulated data for yield improvement studies including quality control and circuit redesign.

摘要翻译： 通过使用相应芯片上的预设标记，将缺陷扫描仪校准到晶片上的每个晶片，可以改善光散射缺陷扫描仪和图案匹配缺陷扫描仪的缺陷扫描仪灵敏度和精度。 标记具有基于缺陷扫描器的灵敏度和相对于相应管芯上的电路图案的预定位置的预定尺寸。 缺陷扫描仪与特定模具的对准提供了相对于整个晶片的对准的坐标精度的改进。 布图映射缺陷过滤系统收集缺陷扫描数据并确定检测到的缺陷与电路布局之间的相互作用。 布图映射缺陷过滤系统实时提供自动识别杀伤性缺陷，导致完成的集成电路故障，并对缺陷进行分类和分析，以识别特定缺陷类别中的潜在杀伤缺陷，以识别有缺陷的裸片。 该系统提供准确的产量估算，以确定生产的晶片是否应该被报废，并且还提供用于产量改进研究的累积数据，包括质量控制和电路重新设计。

公开(公告)号：US5896294A

公开(公告)日：1999-04-20

申请号：US815353

申请日：1997-03-11

申请人： Wanyee Apple Chow ,  Ming C. Chen ,  Yung-Tao Lin ,  Ying Shiau

发明人： Wanyee Apple Chow ,  Ming C. Chen ,  Yung-Tao Lin ,  Ying Shiau

IPC分类号： G05B19/418 ,  G06F19/00 ,  G06G7/64 ,  G06G7/66

CPC分类号： G05B19/41875 ,  Y02P90/14 ,  Y02P90/18 ,  Y02P90/22

摘要： An apparatus and method for selecting products to inspect for defects performs in-situ monitoring of a processing tool during a manufacturing processing step. The data from the in-situ monitoring for a test run of products is correlated by a neural network with data collected during inspection of the test products for defects. During a production run of products, the in-situ monitor data is provided to the neural network which, based on the input data and the correlation, predicts the values of the data that would be collected upon inspection of the products. Specific products from the production run are selected for inspection based upon the predicted values.

摘要翻译： 用于选择检查缺陷的产品的装置和方法在制造处理步骤期间执行对处理工具的原位监测。 来自产品测试运行的现场监测的数据通过神经网络与在检查产品缺陷检查期间收集的数据相关联。 在产品的生产运行期间，将原位监测数据提供给神经网络，神经网络根据输入数据和相关性预测在检查产品时收集的数据的值。 根据预测值选择生产运行中的具体产品进行检查。

公开(公告)号：US5716856A

公开(公告)日：1998-02-10

申请号：US517960

申请日：1995-08-22

申请人： Yung-Tao Lin ,  Zhi-Min Ling ,  James Pak ,  Ying Shiau

发明人： Yung-Tao Lin ,  Zhi-Min Ling ,  James Pak ,  Ying Shiau

IPC分类号： H01L21/66

CPC分类号： H01L22/20 ,  Y10S148/162

摘要： An arrangement and method for detecting sequential processing effects on products to be manufactured in a manufacturing process orders a first set of the products in a first specified processing sequence for a first process step in the manufacturing process. In order to prevent any positional trend created at one process step from being carried over into the next process step, the first set of the products is re-ordered into a second, different specified processing sequence for a second process step in the manufacturing process. Data regarding responses of the first set of the products to the process steps are extracted. The extracted data are correlated with the first and second processing sequences and data analysis is performed on the correlated extracted data. These steps are repeated for subsequent sets of the products, so that although the specified processing sequence is different for each of the individual process steps for a set of products, the same processing sequences for the individual processing steps are used for subsequent sets of the products to be manufactured. Since the processing sequences are not randomized from set to set and do not have to be provided to a database, the amounts of interfacing and disk storage needed are greatly reduced.

公开(公告)号：US06703659B2

公开(公告)日：2004-03-09

申请号：US10338221

申请日：2003-01-08

申请人： Tze Ho Semon Chan ,  Yung-Tao Lin

发明人： Tze Ho Semon Chan ,  Yung-Tao Lin

IPC分类号： H01L2976

CPC分类号： H01L29/66492 ,  H01L21/26586 ,  H01L21/28273 ,  H01L29/66659 ,  H01L29/66825 ,  H01L29/7835 ,  H01L29/7885

摘要： A new method of fabricating and programming and erasing a Flash EEPROM memory cell is achieved. A semiconductor substrate is provided. A tunneling oxide layer is formed overlying said semiconductor substrate. A first polysilicon layer is deposited overlying the tunneling oxide layer. An interpoly oxide layer is deposited overlying the first polysilicon layer. A second polysilicon layer is deposited overlying the interpoly oxide layer. The second polysilicon layer, the interpoly oxide layer, the first polysilicon layer, and the tunneling oxide layer are patterned to form control gates and floating gates for planned Flash EEPROM memory cells. Ions are implanted to form drain junctions for planned Flash EEPROM memory cells in the semiconductor substrate where the drain junctions are shallow and abrupt. Ions are implanted to form angled pocket junctions adjacent to the drain junctions. The angled pocket junctions are implanted at a non-perpendicular angle with respect to the semiconductor substrate and are counter-doped to the drain junctions. Ions are implanted to form source junctions where the junctions are deeper and less abrupt than the drain junctions to complete the Flash EEPROM memory cells in the integrated circuit device.

摘要翻译： 实现了一种制造和编程和擦除闪存EEPROM存储单元的新方法。 提供半导体衬底。 形成覆盖所述半导体衬底的隧道氧化物层。 沉积在隧道氧化物层上的第一多晶硅层。 沉积在第一多晶硅层上的多晶硅层。 第二多晶硅层沉积在层间氧化物层的上方。 对第二多晶硅层，多晶硅氧化物层，第一多晶硅层和隧道氧化物层进行图案化以形成用于计划的闪存EEPROM存储单元的控制栅极和浮置栅极。 离子被植入以形成半导体衬底中计划的闪存EEPROM存储单元的漏极结，其中漏极接点较浅而突然。 植入离子以形成与排水结相邻的倾斜的袋结。 成角度的凹穴接合部以相对于半导体衬底的非垂直角注入，并且与掺杂的漏极结相反。 离子被植入以形成其中结点比漏极结更深并且不太突然的源结，以完成集成电路器件中的闪存EEPROM存储单元。