公开(公告)号：US5673426A

公开(公告)日：1997-09-30

申请号：US484795

申请日：1995-06-07

申请人： Gene W. Shen ,  John Szeto ,  Michael C. Shebanow

发明人： Gene W. Shen ,  John Szeto ,  Michael C. Shebanow

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F11/14 ,  G06F7/46

CPC分类号： G06F9/3004 ,  G06F11/1407 ,  G06F9/30043 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865

摘要： An out of program control order execution data processor that comprises an issue unit, execution means, a floating point exception unit a precise state unit, a floating point status register, and writing means. The issue unit issues instructions in program control order for execution. The issued instructions include floating point instructions and non-floating point instructions. The execution means executes the issued instructions such that at least the floating point instructions may be executed out of program control order by the execution means. The floating point exception unit includes a data storage structure including storage elements. Each issued instruction corresponds to one of the storage elements. Each storage element has a floating point instruction identifying field and a floating point trap type field. The floating point exception unit also includes first logic to write, for each issued instruction, data in the floating point instruction identifying field of the corresponding storage element which indicates whether or not the corresponding issued instruction is a floating point instruction. It further includes second logic to write, for each issued floating point instruction which causes during execution one or more floating point execution exceptions that will result in a corresponding one of a plurality of predefined types of floating point execution traps, data in the floating point trap type field of the corresponding storage element which identifies the one of the predefined types of floating point execution traps that will result. The precise state means retires each issued instruction which does not cause an execution exception during execution and for which all issued instructions preceding it in program control order have been retired. When a first one of the predefined execution exceptions is caused by an issued instruction, the execution means continues execution of issued instructions and the precise state means engages in execution trap sequencing by continuing to retire issued instructions until it encounters an issued instruction that cannot be retired. The issued instruction that cannot be retired being one of (a) the issued instruction that caused the first execution exception, and (b) an issued instruction that was issued earlier than the issued instruction that caused the first execution exception but which caused a second execution exception occurring later than the first execution exception. The floating point status register has a floating point trap type field. The writing means writes data to the floating point trap type field of the floating point status register which identifies the type of floating point execution trap identified by the data in the floating point trap type field of the storage element corresponding to the instruction that cannot be retired when the data in the floating point identifying field of the storage element corresponding to the instruction that cannot be retired indicates that the instruction that cannot be retired is a floating point instruction.

公开(公告)号：US5673408A

公开(公告)日：1997-09-30

申请号：US472394

申请日：1995-06-07

申请人： Michael C. Shebanow ,  Hideki Osone

发明人： Michael C. Shebanow ,  Hideki Osone

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F11/14 ,  G06F9/00 ,  G06F9/30

CPC分类号： G06F9/3004 ,  G06F11/1407 ,  G06F9/30043 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865

摘要： A data processor and associated method for taking and returning from traps speculatively. The data processor supports a predefined number of trap levels for taking nested traps each having a corresponding trap level. The data processor comprises means to form checkpoints, means to back up to the checkpoints, means to take a trap, means to return from a trap, registers, and a trap stack unit. The registers have contents that define the state of the data processor each time a trap is taken. The trap stack unit includes a trap stack data storage structure that has a greater number of trap slack storage entries than there are trap levels. It also includes a freelist unit that maintains a current availability list of the trap stack storage entries that are currently available for mapping to one of the trap levels. The freelist unit identifies, each time a trap is taken, a next one of the currently available trap stack storage entries for mapping to the corresponding one of the trap levels. The trap stack unit further includes read/write logic that writes, for each trap taken, the contents of the registers to the next one of the currently available trap stack storage entries. It still further includes rename mapping logic that maintains a current mapping of each trap level to one of the trap stack storage entries. The rename mapping logic replaces, each time a trap is taken, an old mapping of the corresponding trap level to one of the trap stack storage entries with a current mapping of the corresponding trap level to the next one of the currently available trap stack storage entries. The trap stack unit also includes a resource reclaim unit that maintains an unavailability list of each trap stack storage entry not currently mapped to one of the trap levels by the current mappings but unavailable for mapping to one of the trap levels. The resource reclaim unit adds to the unavailability list, each time a trap is taken, the trap stack storage entry that was mapped to the corresponding trap level by the old mapping and removing from the unavailability list, each time a taken trap can no longer be undone, the trap stack storage entry that was mapped to the corresponding trap level by the old mapping. The freelist unit adds each trap stack storage entry removed from the unavailability list to the current availability list. Finally, the trap stack unit includes a checkpoint storage unit that includes checkpoint storage entries. Each formed checkpoint has a corresponding checkpoint storage entry so that the checkpoint storage unit stores, for each formed checkpoint, the current mappings of the rename mapping logic and the current availability list of the freelist unit in the corresponding checkpoint storage entry. For each backup to a checkpoint, the rename mapping logic replaces the current mappings it maintains with the mappings stored in the corresponding checkpoint storage entry and the freelist unit replaces the current availability list it maintains with the availability list stored in the corresponding checkpoint storage entry.

公开(公告)号：US4667326A

公开(公告)日：1987-05-19

申请号：US685018

申请日：1984-12-20

申请人： Mark S. Young ,  John Drew ,  Michael C. Shebanow

发明人： Mark S. Young ,  John Drew ,  Michael C. Shebanow

IPC分类号： G06F11/10 ,  G11B20/18 ,  H03M13/15 ,  H03M13/27 ,  G06F11/08 ,  G06F11/16

CPC分类号： H03M13/2789 ,  G06F11/10 ,  G11B20/1833 ,  H03M13/15

摘要： A method and apparatus for generating a check sum and a syndrome for detecting errors in a series of bytes comprising a plurality of stages, each stage comprising a plurality of networks of exclusive OR gates, a memory and an exclusive OR gate for exclusively ORing the outputs of the networks resulting from a byte transmitted therethrough with the results stored in a memory in a previous stage due to a previous byte. Each of the stages and the networks therein correspond to a term in a Reed-Solomon polynomial. Except for differences in the number and construction of the networks in each stage, each of the stages are substantially identical and can be selectively used for detecting single and double burst errors.

摘要翻译： 一种用于产生校验和和校正子的方法和装置，用于检测包括多个级的一系列字节中的错误，每个级包括多个异或门的网络，存储器和异或门，用于将输出异或 由前一个字节在前一阶段存储在存储器中的结果产生的网络所产生的网络。 其中每个级和其中的网络对应于Reed-Solomon多项式中的项。 除了每个阶段的网络数量和结构的差异外，每个阶段基本相同，并且可以选择性地用于检测单和双脉冲串错误。

公开(公告)号：US08947444B1

公开(公告)日：2015-02-03

申请号：US12331307

申请日：2008-12-09

申请人： Ziyad S. Hakura ,  Emmett M. Kilgariff ,  Michael C. Shebanow ,  James C. Bowman ,  Philip Browning Johnson ,  Johnny S. Rhoades ,  Rohit Gupta

发明人： Ziyad S. Hakura ,  Emmett M. Kilgariff ,  Michael C. Shebanow ,  James C. Bowman ,  Philip Browning Johnson ,  Johnny S. Rhoades ,  Rohit Gupta

IPC分类号： G06T1/00

CPC分类号： G06T1/20

摘要： A data structure that includes pointers to vertex attributes and primitive descriptions is generated and then processed within a general processing cluster. The general processing cluster includes a vertex attribute fetch unit that fetches from memory vertex attributes corresponding to the vertices defined by the primitive descriptions.

摘要翻译： 生成包含指向顶点属性和原始描述的指针的数据结构，然后在通用处理集群中进行处理。 一般处理集群包括从与由原始描述定义的顶点相对应的存储器顶点属性中获取的顶点属性提取单元。

公开(公告)号：US08533435B2

公开(公告)日：2013-09-10

申请号：US12875843

申请日：2010-09-03

申请人： Xiaogang Qiu ,  Ming Y. Siu ,  Yan Yan Tang ,  John Erik Lindholm ,  Michael C. Shebanow ,  Stuart F. Oberman

发明人： Xiaogang Qiu ,  Ming Y. Siu ,  Yan Yan Tang ,  John Erik Lindholm ,  Michael C. Shebanow ,  Stuart F. Oberman

IPC分类号： G06F9/34

CPC分类号： G06F9/3012 ,  G06F9/30098 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889

摘要： One embodiment of the present invention sets forth a technique for collecting operands specified by an instruction. As a sequence of instructions is received the operands specified by the instructions are assigned to ports, so that each one of the operands specified by a single instruction is assigned to a different port. Reading of the operands from a multi-bank register file is scheduled by selecting an operand from each one of the different ports to produce an operand read request and ensuring that two or more of the selected operands are not stored in the same bank of the multi-bank register file. The operands specified by the operand read request are read from the multi-bank register file in a single clock cycle. Each instruction is then executed as the operands specified by the instruction are read from the multi-bank register file and collected over one or more clock cycles.

摘要翻译： 本发明的一个实施例提出了一种用于收集由指令指定的操作数的技术。 由于接收到指令序列，指令指定的操作数被分配给端口，以便将由单个指令指定的每个操作数分配给不同的端口。 通过从不同端口中的每一个选择一个操作数来调度来自多存储器寄存器文件的操作数，以产生操作数读取请求，并确保所选择的操作数中的两个或更多个不存储在多个存储区的同一个存储区中 银行寄存器文件。 由操作数读取请求指定的操作数在单个时钟周期内从多存储体寄存器文件读取。 然后由指令指定的操作数从多存储寄存器文件中读取并在一个或多个时钟周期内采集，执行每条指令。

公开(公告)号：US20110078358A1

公开(公告)日：2011-03-31

申请号：US12858362

申请日：2010-08-17

申请人： Michael C. Shebanow

发明人： Michael C. Shebanow

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/1045

摘要： One embodiment of the present invention sets forth a technique for computing virtual addresses for accessing thread data. Components of the complete virtual address for a thread group are used to determine whether or not a cache line corresponding to the complete virtual address is not allocated in the cache. Actual computation of the complete virtual address is deferred until after determining that a cache line corresponding to the complete virtual address is not allocated in the cache.

摘要翻译： 本发明的一个实施例提出了一种用于计算用于访问线程数据的虚拟地址的技术。 用于线程组的完整虚拟地址的组件用于确定与完整虚拟地址相对应的高速缓存行是否未分配在高速缓存中。 在确定与完整虚拟地址相对应的高速缓存线未分配在高速缓存中之前，完整的虚拟地址的实际计算被推迟。

公开(公告)号：US20110072243A1

公开(公告)日：2011-03-24

申请号：US12875843

申请日：2010-09-03

申请人： Xiaogang Qiu ,  Ming Y. Siu ,  Yan Yan Tang ,  John Erik Lindholm ,  Michael C. Shebanow ,  Stuart F. Oberman

发明人： Xiaogang Qiu ,  Ming Y. Siu ,  Yan Yan Tang ,  John Erik Lindholm ,  Michael C. Shebanow ,  Stuart F. Oberman

IPC分类号： G06F9/30

CPC分类号： G06F9/3012 ,  G06F9/30098 ,  G06F9/3824 ,  G06F9/3851 ,  G06F9/3885 ,  G06F9/3887 ,  G06F9/3889

摘要： One embodiment of the present invention sets forth a technique for collecting operands specified by an instruction. As a sequence of instructions is received the operands specified by the instructions are assigned to ports, so that each one of the operands specified by a single instruction is assigned to a different port. Reading of the operands from a multi-bank register file is scheduled by selecting an operand from each one of the different ports to produce an operand read request and ensuring that two or more of the selected operands are not stored in the same bank of the multi-bank register file. The operands specified by the operand read request are read from the multi-bank register file in a single clock cycle. Each instruction is then executed as the operands specified by the instruction are read from the multi-bank register file and collected over one or more clock cycles.

摘要翻译： 本发明的一个实施例提出了一种用于收集由指令指定的操作数的技术。 由于接收到指令序列，指令指定的操作数被分配给端口，以便将由单个指令指定的每个操作数分配给不同的端口。 通过从不同端口中的每一个选择一个操作数来调度来自多存储器寄存器文件的操作数，以产生操作数读取请求，并确保所选择的操作数中的两个或更多个不存储在多个存储区的同一个存储区中 银行寄存器文件。 由操作数读取请求指定的操作数在单个时钟周期内从多存储体寄存器文件读取。 然后由指令指定的操作数从多存储寄存器文件中读取并在一个或多个时钟周期内采集，执行每条指令。

公开(公告)号：US5675759A

公开(公告)日：1997-10-07

申请号：US522567

申请日：1995-09-01

申请人： Michael C. Shebanow ,  Gene W. Shen ,  Ravi Swami ,  Niteen A. Patkar

发明人： Michael C. Shebanow ,  Gene W. Shen ,  Ravi Swami ,  Niteen A. Patkar

IPC分类号： G06F9/38

CPC分类号： G06F9/384 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863

摘要： In a microprocessor, an apparatus is included for coordinating the use of physical registers in the microprocessor. Upon receiving an instruction, the coordination apparatus extracts source and destination logical registers from the instruction. For the destination logical register, the apparatus assigns a physical address to correspond to the logical register. In so doing, the apparatus stores the former relationship between the logical register and another physical register. Storing this former relationship allows the apparatus to backstep to a particular instruction when an execution exception is encountered. Also, the apparatus checks the instruction to determine whether it is a speculative branch instruction. If so, then the apparatus creates a checkpoint by storing selected state information. This checkpoint provides a reference point to which the processor may later backup if it is determined that a speculated branch was incorrectly predicted. Overall, the apparatus coordinates the use of physical registers in the processor in such a way that: (1) logical/physical register relationships are easily changeable; and (2) backup and backstep procedures are accommodated.

摘要翻译： 在微处理器中，包括用于协调微处理器中物理寄存器的使用的装置。 在接收到指令之后，协调装置从指令中提取源和目的地逻辑寄存器。 对于目的地逻辑寄存器，设备分配一个物理地址以对应于逻辑寄存器。 在这样做时，该装置存储逻辑寄存器与另一物理寄存器之间的之前的关系。 存储这种以前的关系允许设备在遇到执行异常时后退到特定的指令。 此外，该装置检查指令以确定它是否是推测性分支指令。 如果是这样，则设备通过存储所选择的状态信息来创建检查点。 如果确定推测的分支被错误地预测，该检查点将提供处理器稍后备份的参考点。 总的来说，该装置协调处理器中物理寄存器的使用，使得：（1）逻辑/物理寄存器关系容易改变; 和（2）备份和后台程序。

公开(公告)号：US5644742A

公开(公告)日：1997-07-01

申请号：US473223

申请日：1995-06-07

申请人： Gene W. Shen ,  John Szeto ,  Niteen A. Patkar ,  Michael C. Shebanow

发明人： Gene W. Shen ,  John Szeto ,  Niteen A. Patkar ,  Michael C. Shebanow

IPC分类号： G06F9/312 ,  G06F9/38 ,  G06F11/14 ,  G06F11/00

CPC分类号： G06F9/3004 ,  G06F11/1407 ,  G06F9/30043 ,  G06F9/3834 ,  G06F9/3836 ,  G06F9/384 ,  G06F9/3842 ,  G06F9/3855 ,  G06F9/3857 ,  G06F9/3863 ,  G06F9/3865

摘要： Time-out checkpoints are formed based on a predetermined time-out condition or interval since the last checkpoint was formed rather than forming a checkpoint to store current processor state based merely on decoded Instruction attributes. Such time-out conditions may include the number of instructions issued or the number of clock cycles elapsed, for example. Time-out checkpointing limits the maximum number of instructions within a checkpoint boundary and bounds the time period for recovery from an exception condition. The processor can restore time-out based checkpointed state faster than an instruction decode based checkpoint technique in the event of an exception so long as the instruction window size is greater than the maximum number of instructions within a checkpoint boundary, end such method eliminates processor state restoration dependency on instruction window size. Time-out checkpoints may be implemented with conventional checkpoints, or in a novel logical and physical register rename map checkpointing technique. Timeout checkpoint formation may be used with conventional processor backup techniques as well as with a novel backtracking technique including processor backup and backstepping.

摘要翻译： 基于预定的超时条件或时间间隔形成超时检查点，因为上次检查点形成而不是形成一个检查点，以仅仅基于解码的指令属性来存储当前的处理器状态。 例如，这种超时条件可以包括发出的指令的数量或经过的时钟周期的数量。 超时检查点限制检查点边界内的最大指令数，并限制从异常情况恢复的时间段。 只要指令窗口大小大于检查点边界内的最大指令数，处理器就可以比基于指令解码的检查点技术更快地恢复超时的检查点状态，结束这种方法消除处理器状态 恢复依赖于指令窗口大小。 超时检查点可以用常规检查点或新颖的逻辑和物理寄存器重命名映射检查点技术来实现。 超时检查点的形成可以与常规的处理器备份技术一起使用，还可以使用包括处理器备份和后台步骤的新型回溯技术。

公开(公告)号：US5367494A

公开(公告)日：1994-11-22

申请号：US113632

申请日：1993-08-31

申请人： Michael C. Shebanow ,  Mitchell K. Alsup ,  Hunter L. Scales ,  George P. Hoekstra

发明人： Michael C. Shebanow ,  Mitchell K. Alsup ,  Hunter L. Scales ,  George P. Hoekstra

IPC分类号： G11C11/41 ,  G11C7/10 ,  G11C8/12 ,  G11C11/00 ,  G11C11/401 ,  G11C8/00 ,  G11C7/00

CPC分类号： G11C8/12 ,  G11C11/005 ,  G11C7/1042

摘要： A memory device (28) executes memory access operations of two or more storage locations concurrently. The memory device (28) is comprised of a plurality of memory bank decode logic circuits (30, 32, 56) and a plurality of memory banks (34, 52). Each of the decode logic circuits decodes a first information and control signal set to enable a first memory bank to begin and complete a memory access operation. Each memory bank is comprised of a plurality of latch circuits (39,40, 42, 50) to store a predetermined information and control signal set necessary to perform the memory access operation. A second control signal and information set may, therefore, enable a second memory bank within the memory device (28) to perform a second memory access operation concurrently in time with the first memory access operation.

摘要翻译： 存储器装置（28）同时执行两个或多个存储位置的存储器存取操作。 存储器件（28）由多个存储体解码逻辑电路（30,32,56）和多个存储器组（34,52）组成。 每个解码逻辑电路解码设置的第一信息和控制信号，以使第一存储体开始并完成存储器访问操作。 每个存储体由多个锁存电路（39,40,42,50）组成，以存储执行存储器访问操作所必需的预定信息和控制信号。 因此，第二控制信号和信息集可以使存储器装置（28）内的第二存储器组能够在第一存储器存取操作的同时执行第二存储器存取操作。