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28 条记录 (耗时 0.019 秒)

    Method to improve current and slew rate ratio of off-chip drivers
    21.
    发明申请
    Method to improve current and slew rate ratio of off-chip drivers 有权
    提高片外驱动器的电流和转换速率比的方法

    公开(公告)号：US20060125520A1

    公开(公告)日：2006-06-15

    申请号：US11012777

    申请日：2004-12-14

    申请人： Thoai Le ,  George Alexander

    发明人： Thoai Le ,  George Alexander

    IPC分类号： H03K19/00

    CPC分类号： H03K19/00323 ,  H03K19/00384

    摘要： An off-chip driver (OCD) circuit and technique to reduce skew between rising and falling edges of output signals as process conditions vary are provided. Variations in process conditions may result in stronger or weaker relative current drive between NMOS and PMOS transistors. One or more process-dependent compensating current paths may be added to conventional pull-up and/or pull-down current paths to compensate for process variations by supplementing the current drive of transistors used to charge (PMOS) or discharge (NMOS) an output node of and end driver (e.g., inverter) stage of an OCD.

    摘要翻译： 提供了片上驱动器（OCD）电路和技术，以减少输出信号的上升沿和下降沿之间的偏差，因为过程条件变化。 工艺条件的变化可能导致NMOS和PMOS晶体管之间更强或更弱的相对电流驱动。 一个或多个处理相关的补偿电流路径可以被添加到传统的上拉和/或下拉电流路径中，以通过补充用于对PMOS（或PMOS）或放电（NMOS）的输出的晶体管的电流驱动来补偿过程变化 OCD的节点和终端驱动器（例如，逆变器）级。

    Memory device and method of reading data from a memory device
    22.
    发明授权
    Memory device and method of reading data from a memory device 失效
    从存储器件读取数据的存储器件和方法

    公开(公告)号：US06970395B2

    公开(公告)日：2005-11-29

    申请号：US10658130

    申请日：2003-09-08

    申请人： Thoai-Thai Le ,  Ralf Klein ,  Eckhard Brass ,  George Alexander

    发明人： Thoai-Thai Le ,  Ralf Klein ,  Eckhard Brass ,  George Alexander

    IPC分类号： G11C7/10 ,  G11C11/4076 ,  G11C8/00

    CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1072 ,  G11C2207/2281

    摘要： A memory device includes a delay-locked loop circuit having delay elements and a synchronization circuit coupled to the delay-locked loop circuit. The synchronization circuit receives a synchronization enable signal and outputs a plurality of enable signals, including an enable signal coupled to an output circuit. Because the enable signal is synchronized with the read signal, it is possible to provide more time to read data into the buffer. A method of reading data from a memory device couples a synchronization enable signal and an external clock signal to a synchronization circuit. A read signal and an output enable are generated based upon a synchronization enable signal and a delayed clock signal of the external clock signal. Because the output signal is synchronized to the read signal, more time is allowed for the sense function.

    摘要翻译： 存储器件包括具有延迟元件的延迟锁定环路电路和耦合到延迟锁定环路电路的同步电路。 同步电路接收同步使能信号并输出​​多个使能信号，包括耦合到输出电路的使能信号。 由于使能信号与读取信号同步，所以可以提供更多的时间将数据读入缓冲器。 从存储器件读取数据的方法将同步使能信号和外部时钟信号耦合到同步电路。 基于外部时钟信号的同步使能信号和延迟的时钟信号，产生读取信号和输出使能。 由于输出信号与读取信号同步，所以允许感应功能更多的时间。

    Systems and Methods for Reservations of Charging Stations for Electric Vehicles
    23.
    发明申请
    Systems and Methods for Reservations of Charging Stations for Electric Vehicles 审中-公开
    电动车辆充电站预约系统及方法

    公开(公告)号：US20120296678A1

    公开(公告)日：2012-11-22

    申请号：US13112438

    申请日：2011-05-20

    申请人： John Christopher Boot ,  Aleksandar Vukojevic ,  George Alexander

    发明人： John Christopher Boot ,  Aleksandar Vukojevic ,  George Alexander

    IPC分类号： G06Q10/00

    CPC分类号： G06Q10/02

    摘要： Systems and methods may enable customers to reserve time slots at charging stations for recharging electric vehicles. The systems and methods may include receiving, from a customer computing device associated with a customer, a reservation inquiry to access a charging station to recharge an electric vehicle; providing, to the customer computing device, a respective cost for accessing the charging station during one or more available time periods; receiving a selection from the customer computing device for at least a portion of the available time periods; and delivering, to the customer computing device, a reservation confirmation for the selected time period.

    摘要翻译： 系统和方法可以使客户能够在充电站预留时隙以为电动车充电。 系统和方法可以包括从与客户相关联的客户计算设备接收预约查询以访问充电站以对电动车辆再充电; 向所述客户计算设备提供在一个或多个可用时间段内访问所述充电站的相应成本; 从所述客户计算设备接收可用时间段的至少一部分的选择; 以及向所述客户计算设备递送所选择的时间段的预约确认。

    Maintaining internal voltages of an integrated circuit in response to a clocked standby mode
    24.
    发明申请
    Maintaining internal voltages of an integrated circuit in response to a clocked standby mode 有权
    响应时钟待机模式，保持集成电路的内部电压

    公开(公告)号：US20070025163A1

    公开(公告)日：2007-02-01

    申请号：US11194302

    申请日：2005-08-01

    申请人： Torsten Partsch ,  George Alexander ,  Ben Heilmann ,  David Herbert

    发明人： Torsten Partsch ,  George Alexander ,  Ben Heilmann ,  David Herbert

    IPC分类号： G11C5/14

    CPC分类号： G11C5/147

    摘要： A method and circuit for controlling an output reference voltage generated by a reference voltage generator disposed on a memory device are provided. A signal for enabling a clocked standby mode of the memory device is received. If the signal indicates that the memory device is in the clocked standby mode, a first reference voltage is generated as the output reference voltage of the reference voltage generator using a first voltage. If the signal indicates that the memory device is not in the clocked standby mode, a second reference voltage is generated as the output reference voltage of the reference voltage generator using a second voltage.

    摘要翻译： 提供一种用于控制由设置在存储器件上的参考电压发生器产生的输出参考电压的方法和电路。 接收用于启用存储器件的时钟待机模式的信号。 如果信号指示存储器件处于时钟待机模式，则使用第一电压产生第一参考电压作为参考电压发生器的输出参考电压。 如果信号指示存储器件未处于时钟待机模式，则使用第二电压产生第二参考电压作为参考电压发生器的输出参考电压。

    Self alignment system for complement clocks
    26.
    发明授权
    Self alignment system for complement clocks 失效
    补码时钟自对准系统

    公开(公告)号：US06946889B2

    公开(公告)日：2005-09-20

    申请号：US10364716

    申请日：2003-02-11

    申请人： Thoai-Thai Le ,  George Alexander ,  Guenter Gerstmeier

    发明人： Thoai-Thai Le ,  George Alexander ,  Guenter Gerstmeier

    IPC分类号： G01D18/00 ,  G06F1/04 ,  G06F1/12 ,  H03K5/06 ,  H03K5/151 ,  H03K5/153

    CPC分类号： H03K5/151 ,  G06F1/12

    摘要： A self-alignment system for complement clock signals includes a first delay circuit and a second delay circuit. A first clock signal may be propagated through the first delay circuit and a second clock signal may be propagated through the second delay circuit. A propagation delay of each of the first and second delay circuits may be selectively varied as a function of the first and second clock signals.

    摘要翻译： 用于补码时钟信号的自对准系统包括第一延迟电路和第二延迟电路。 第一时钟信号可以通过第一延迟电路传播，并且第二时钟信号可以通过第二延迟电路传播。 可以根据第一和第二时钟信号来选择性地改变第一和第二延迟电路中的每一个的传播延迟。

    Memory device and method of reading data from a memory device
    27.
    发明申请
    Memory device and method of reading data from a memory device 失效
    从存储器件读取数据的存储器件和方法

    公开(公告)号：US20050052943A1

    公开(公告)日：2005-03-10

    申请号：US10658130

    申请日：2003-09-08

    申请人： Thoai-Thai Le ,  Ralf Klein ,  Eckhard Brass ,  George Alexander

    发明人： Thoai-Thai Le ,  Ralf Klein ,  Eckhard Brass ,  George Alexander

    IPC分类号： G11C7/10 ,  G11C11/4076 ,  G11C8/00

    CPC分类号： G11C11/4076 ,  G11C7/1051 ,  G11C7/1072 ,  G11C2207/2281

    摘要： The present invention relates to a memory device which enables a greater amount of time to read data into a buffer. In particular, a memory device according to one aspect of the present invention comprises a delay-locked loop circuit having a plurality of delay elements and a synchronization circuit coupled to the delay-locked loop circuit. The synchronization circuit also receives a synchronization enable signal and outputs a plurality of enable signals, including an enable signal coupled to an output circuit. Because the enable signal coupled to the output circuit is synchronized with the read signal, it is possible to provide more time to read data into the buffer. According to another aspect of the present invention, a method of reading data from a memory device couples a synchronization enable signal to a synchronization circuit. An external clock signal is also coupled to a delay-locked loop circuit. A read signal is generated based upon a synchronization enable signal and a delayed clock signal of the external clock signal. An output enable is also generated based upon the synchronization enable signal and a delayed clock signal of the external clock signal. Because the output signal is synchronized to the read signal, more time is allowed for the sense function.

    摘要翻译： 本发明涉及一种能够将数据读入缓冲器的时间更长的存储器件。 特别地，根据本发明的一个方面的存储器件包括具有多个延迟元件的延迟锁定环路电路和耦合到延迟锁定环路电路的同步电路。 同步电路还接收同步使能信号并输出​​多个使能信号，包括耦合到输出电路的使能信号。 由于耦合到输出电路的使能信号与读取信号同步，所以可以提供更多的时间将数据读入缓冲器。 根据本发明的另一方面，一种从存储器件读取数据的方法将同步使能信号耦合到同步电路。 外部时钟信号也耦合到延迟锁定环路电路。 基于外部时钟信号的同步使能信号和延迟的时钟信号产生读取信号。 还基于同步使能信号和外部时钟信号的延迟时钟信号产生输出使能。 由于输出信号与读取信号同步，所以允许感应功能更多的时间。