公开(公告)号：US20090231929A1

公开(公告)日：2009-09-17

申请号：US12396243

申请日：2009-03-02

申请人： Hideaki Miyamoto

发明人： Hideaki Miyamoto

IPC分类号： G11C7/10 ,  G11C8/00

CPC分类号： G11C11/22 ,  G11C5/143 ,  G11C5/144 ,  G11C5/147 ,  G11C8/08

摘要： A memory includes a first holding circuit holding a first address of first data, a second holding circuit holding at least one of a second address of the first data and the amount of the first data, and an operation control circuit performing an operation rewriting the first address, an operation rewriting the second address or the amount of the first data and an operation continuously holding the first address and the second address or the amount of the first data.

摘要翻译： 存储器包括保持第一数据的第一地址的第一保持电路，保持第一数据的第二地址和第一数据的量中的至少一个的第二保持电路，以及执行重写第一数据的操作的操作控制电路 地址，重写第二地址或第一数据量的操作以及持续保持第一地址和第二地址或第一数据量的操作。

公开(公告)号：US20090175528A1

公开(公告)日：2009-07-09

申请号：US12351094

申请日：2009-01-09

申请人： Hideaki Miyamoto

发明人： Hideaki Miyamoto

IPC分类号： G06K9/00

CPC分类号： G06T5/009 ,  G06T7/12 ,  G06T7/174 ,  G06T2207/10121 ,  G06T2207/10144 ,  G06T2207/20224 ,  G06T2207/30004

摘要： An image processing apparatus is provided. The apparatus includes a setting unit configured to set a radiation exposure condition; a radiation generation unit configured to generate a radiation beam according to the radiation exposure condition; a two-dimensional radiation sensor configured to transform the reached radiation beam into a radiation image data and output the radiation image data; a storage unit configured to store the radiation image data; a detecting unit configured to detect a scattered radiation fluctuation in the reached radiation beam based on a comparison of two radiation image data with different radiation exposure condition, where the two radiation image data are selected within the plurality of radiation image data stored in the storage unit; and an image processing unit configured to extract a outline of a region of interest from the radiation image data based on the scattered radiation fluctuation detected by the detecting unit.

摘要翻译： 提供一种图像处理装置。 该装置包括设置单元，其被配置为设置辐射曝光条件; 辐射生成单元，被配置为根据所述辐射照射条件产生辐射束; 二维辐射传感器，被配置为将到达的辐射束变换成辐射图像数据并输出放射线图像数据; 存储单元，被配置为存储所述放射线图像数据; 检测单元，被配置为基于两个辐射图像数据与不同的曝光条件的比较来检测所达到的辐射束中的散射辐射波动，其中在存储在存储单元中的多个辐射图像数据中选择两个辐射图像数据 ; 以及图像处理单元，被配置为基于由所述检测单元检测到的散射辐射波动，从所述放射线图像数据中提取感兴趣区域的轮廓。

公开(公告)号：US07423925B2

公开(公告)日：2008-09-09

申请号：US11473083

申请日：2006-06-23

申请人： Hideaki Miyamoto

发明人： Hideaki Miyamoto

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40603

摘要： A memory capable of performing a refresh operation uncompetitively with an internal access operation also when an external access operation is non-cyclically performed is obtained. This memory comprises an external access detection portion detecting an external access operation, an access control portion performing an internal access operation on the basis of the external access operation and a refresh determination portion determining whether or not to perform a refresh operation on the basis of detection of the external access operation by the external access detection portion and the operating state of the access control portion. The access control portion performs the refresh operation before or after the internal access operation on the basis of the result of determination of the refresh determination portion.

摘要翻译： 获得当外部访问操作非周期性地执行时，能够在内部访问操作中无效地执行刷新操作的存储器。 该存储器包括检测外部访问操作的外部访问检测部分，基于外部访问操作执行内部访问操作的访问控制部分以及基于检测来确定是否执行刷新操作的刷新确定部分 的外部访问检测部分的外部访问操作和访问控制部分的操作状态。 访问控制部分基于刷新确定部分的确定结果在内部访问操作之前或之后执行刷新操作。

公开(公告)号：US07397286B2

公开(公告)日：2008-07-08

申请号：US11274298

申请日：2005-11-16

申请人： Hideaki Miyamoto

发明人： Hideaki Miyamoto

IPC分类号： G11C7/00

CPC分类号： G11C19/00 ,  G11C19/28 ,  H03K3/012 ,  H03K3/0372

摘要： A flip-flop circuit capable of inhibiting current consumption as well as the circuit scale from increase is provided. This flip-flop circuit comprises a first latch circuit including first and second inverter circuits. A first power supply line capable of switching a supplied potential between a fixing potential supplied for fixing the potentials of output nodes of the first and second inverter circuits and a floating potential supplied for floating the potentials of the output nodes of the first and second inverter circuits is connected to the first latch circuit.

摘要翻译： 提供了能够抑制电流消耗以及电路规模增加的触发电路。 该触发器电路包括包括第一和第二反相器电路的第一锁存电路。 第一电源线，其能够切换提供的固定电位的供电电位，用于固定第一和第二反相器电路的输出节点的电位，以及提供用于浮置第一和第二反相器电路的输出节点的电位的浮动电位 连接到第一锁存电路。

公开(公告)号：US07362642B2

公开(公告)日：2008-04-22

申请号：US11494748

申请日：2006-07-28

申请人： Hideaki Miyamoto ,  Shigeharu Matsushita

发明人： Hideaki Miyamoto ,  Shigeharu Matsushita

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40603 ,  G11C2211/4061

摘要： A memory allowing reduction of the period of an external access operation is provided. This memory comprises an access control portion performing an internal access operation on the basis of an external access operation, a refresh control portion performing a refresh operation and a refresh division control portion dividing the refresh operation into a read operation RFRD and rewrite operations RFRS1 and RFRS2. The memory performs the read operation RFRD and the rewrite operations RFRS1 and RFRS2 at least either before or after different internal access operations corresponding to different external access operations respectively.

摘要翻译： 提供了允许减少外部访问操作的周期的存储器。 该存储器包括访问控制部分，其基于外部访问操作执行内部访问操作，执行刷新操作的刷新控制部分和将刷新操作分为读取操作RFRD和重写操作RFRS 1的刷新分配控制部分，以及 RFRS 2。 存储器分别在对应于不同外部访问操作的不同内部访问操作之前或之后至少执行读取操作RFRD和重写操作RFRS 1和RFRS 2。

公开(公告)号：US07319606B2

公开(公告)日：2008-01-15

申请号：US11090660

申请日：2005-03-28

申请人： Hideaki Miyamoto

发明人： Hideaki Miyamoto

IPC分类号： G11C11/22

CPC分类号： G11C11/005 ,  G11C14/0072

摘要： A memory capable of effectively reducing the chip size not only by sharing a read/write circuit but also by reducing a memory cell size is provided. This memory comprises a first memory cell array having a plurality of first memory cells, a second memory cell array having a plurality of second memory cells different in type from the first memory cells and a selection control circuit provided separately from the first memory cell array and the second memory cell array for controlling selection of either the first memory cell array or the second memory cell array.

摘要翻译： 提供了一种能够不仅通过共享读/写电路而且通过减少存储单元尺寸有效地减小芯片尺寸的存储器。 该存储器包括具有多个第一存储器单元的第一存储单元阵列，具有与第一存储单元类型不同的多个第二存储单元的第二存储单元阵列和与第一存储单元阵列分开设置的选择控制电路， 用于控制第一存储单元阵列或第二存储单元阵列的选择的第二存储单元阵列。

公开(公告)号：US20070025172A1

公开(公告)日：2007-02-01

申请号：US11494748

申请日：2006-07-28

申请人： Hideaki Miyamoto ,  Shigeharu Matsushita

发明人： Hideaki Miyamoto ,  Shigeharu Matsushita

IPC分类号： G11C7/00

CPC分类号： G11C11/406 ,  G11C11/40603 ,  G11C2211/4061

摘要： A memory allowing reduction of the period of an external access operation is provided. This memory comprises an access control portion performing an internal access operation on the basis of an external access operation, a refresh control portion performing a refresh operation and a refresh division control portion dividing the refresh operation into a read operation RFRD and rewrite operations RFRS1 and RFRS2. The memory performs the read operation RFRD and the rewrite operations RFRS1 and RFRS2 at least either before or after different internal access operations corresponding to different external access operations respectively.

摘要翻译： 提供了允许减少外部访问操作的周期的存储器。 该存储器包括访问控制部分，其基于外部访问操作执行内部访问操作，执行刷新操作的刷新控制部分和将刷新操作分为读取操作RFRD和重写操作RFRS 1的刷新分配控制部分，以及 RFRS 2.存储器分别在对应于不同外部访问操作的不同内部访问操作之前或之后至少执行读取操作RFRD和重写操作RFRS 1和RFRS 2。

公开(公告)号：US20050052914A1

公开(公告)日：2005-03-10

申请号：US10932081

申请日：2004-09-02

申请人： Hideaki Miyamoto ,  Naofumi Sakai ,  Yoshiyuki Ishizuka

发明人： Hideaki Miyamoto ,  Naofumi Sakai ,  Yoshiyuki Ishizuka

IPC分类号： H01L27/10 ,  G11C5/02 ,  G11C11/00 ,  G11C11/22 ,  H01L21/8246 ,  H01L27/105

CPC分类号： G11C5/025 ,  G11C11/22

摘要： A semiconductor memory device allowing miniaturization is provided. This semiconductor memory device comprises a word line and a bit line arranged to intersect with each other, a memory cell array region including a plurality of memory cells connected to the word line and the bit line and a transfer gate transistor arranged under the memory cell array region.

摘要翻译： 提供允许小型化的半导体存储器件。 这种半导体存储器件包括一个字线和位线相互交叉排列，一个存储单元阵列区域包括连接到该字线和该位线的多个存储单元，以及一个布置在该存储单元阵列下面的一个传输门晶体管 地区。

公开(公告)号：US20120257809A1

公开(公告)日：2012-10-11

申请号：US13515677

申请日：2010-12-10

申请人： Hideaki Miyamoto

发明人： Hideaki Miyamoto

IPC分类号： G06K9/46

CPC分类号： G06T5/009 ,  A61B6/481 ,  A61B6/486 ,  A61B6/504 ,  G06T5/50 ,  G06T7/13 ,  G06T2207/10016 ,  G06T2207/10121 ,  G06T2207/20192 ,  G06T2207/20224 ,  G06T2207/30101 ,  G06T2207/30104

摘要： A feature value is extracted from a boundary region that is located between a contrast-agent injection region and a background region in a subtraction image, a gradation curve depending on the feature value is generated, and gradation processing is performed by applying the gradation curve to the subtraction image.

摘要翻译： 从减法图像中的造影剂注入区域和背景区域之间的边界区域提取特征值，生成根据特征值的灰度曲线，并且通过将灰度曲线应用于 减法图像。

公开(公告)号：US07733681B2

公开(公告)日：2010-06-08

申请号：US11739336

申请日：2007-04-24

申请人： Hideaki Miyamoto

发明人： Hideaki Miyamoto

IPC分类号： G11C5/06

CPC分类号： G11C11/22

摘要： A memory capable of suppressing increase of the chip area thereof while increasing a read voltage is obtained. This memory comprises a memory cell array including a plurality of subarrays, a sub bit line arranged on each subarray and provided to be connectable to a main bit line, a storage portion connected between the word line and the sub bit line and a first transistor having a gate connected to the sub bit line and a first source/drain region connected to the main bit line for controlling the potential of the main bit line on the basis of the potential of the sub bit line in a read operation.

摘要翻译： 获得能够在增加读取电压的同时抑制其芯片面积的增加的存储器。 该存储器包括一个存储单元阵列，该存储单元阵列包括多个子阵列，一个排列在每个子阵列上并被提供以可连接到主位线的子位线，连接在字线和子位线之间的存储部分以及第一晶体管， 连接到子位线的栅极和连接到主位线的第一源极/漏极区域，用于在读取操作中基于子位线的电位来控制主位线的电位。