公开(公告)号：US20060139694A1

公开(公告)日：2006-06-29

申请号：US11316125

申请日：2005-12-21

申请人： Hideki Ishida ,  Chikara Ishihara ,  Shingo Yoshida

发明人： Hideki Ishida ,  Chikara Ishihara ,  Shingo Yoshida

IPC分类号： H04N1/40

CPC分类号： H04N1/40025 ,  H04N1/4015

摘要： [Object]The object of this invention is to prevent as much as possible the occurrence of uneven image density produced by photoreceptors, in which uneven electrification and uneven sensitivity coexist, without enlargement of an apparatus as well as increase in cost. [Solution]For each of segments of the surface of the photoreceptor, individually memorizing a slope information K1 which defines the slope of when a pixel gradation is approximately linear-transformed into exposure amount, and then, based upon K1 per segment, individually transforming the pixel gradation into the exposure amount (individual exposure amount transformation). The slope information is an information which, with a reference electric potential Vs1, matches the electric potential after the exposure of when the exposure amount, obtained by transforming a reference pixel gradation Is1 by means of the individual exposure amount transformation, is applied to the approximately-linear exposure property excepting the converging region to a residual potential VL, or to the exposure property extending the aforesaid property by extrapolation operation, among exposure property g01 showing correspondence between the exposure amount and the electric potential after exposure per segment.

摘要翻译： 本发明的目的是尽可能地防止不均匀的电气化和不均匀的灵敏度共存的感光体产生的不均匀图像密度的产生，而不会增加设备的增加以及成本的增加。 [解决方案]对于感光体表面的每个段，分别存储限定像素级近似线性变换为曝光量的斜率的斜率信息K 1，然后基于每个段的K 1个别地 将像素等级变换为曝光量（个体曝光量变换）。 斜率信息是将参考电位Vs 1与曝光后的电位相匹配的信息，当将通过单独曝光量变换将参考像素灰度Is 1变换得到的曝光量应用于 在曝光量与暴露每段后的电位之间的对应关系的曝光特性g 01之中，通过外推操作将除会聚区域之外的残留电位VL的近似线性曝光特性或扩展上述性质的曝光性能。

公开(公告)号：US06844773B2

公开(公告)日：2005-01-18

申请号：US10613123

申请日：2003-07-07

申请人： Hideki Ishida ,  Megumi Oono

发明人： Hideki Ishida ,  Megumi Oono

IPC分类号： H01L27/04 ,  G05F3/26 ,  H01L21/822 ,  H03F3/343 ,  H03F3/345 ,  H03F3/45 ,  H03K19/00 ,  G05F1/10

CPC分类号： G05F3/262 ,  H03F3/345 ,  H03F3/4521 ,  H03F2203/45658 ,  H03F2203/45702

摘要： A semiconductor integrated circuit device has a first MIS transistor of a first conductivity type, a second MIS transistor of a second conductivity type, a resistor connected in series between a first power-source line and a second power-source line, and a third MIS transistor of the first conductivity type. The third MIS transistor has a gate connected to a node where the first MIS transistor and the second MIS transistor are connected together, and a drain connected to a connection node where the second MIS transistor and the resistor are connected together.

摘要翻译： 半导体集成电路器件具有第一导电类型的第一MIS晶体管，第二导电类型的第二MIS晶体管，串联连接在第一电源线和第二电源线之间的电阻器，以及第三MIS 第一导电类型的晶体管。 第三MIS晶体管具有连接到第一MIS晶体管和第二MIS晶体管连接在一起的节点的栅极，以及连接到第二MIS晶体管和电阻器连接在一起的连接节点的漏极。

公开(公告)号：US06624706B2

公开(公告)日：2003-09-23

申请号：US09988618

申请日：2001-11-20

申请人： Hirohito Higashi ,  Hideki Ishida

发明人： Hirohito Higashi ,  Hideki Ishida

IPC分类号： H03L706

CPC分类号： H03L7/0805 ,  H03L1/022 ,  H03L7/0893 ,  H03L7/10 ,  H03L7/189

摘要： A bias current IB additionally provided to a current-controlled circuit 13 in a PLL circuit is the sum of bias currents IB1 and IB2 which are generated by a bias adjustment circuit (18, 19, 20, 21 and 22) and a bias current generating circuit (23 and 24), respectively. The bias adjustment circuit adjusts the bias current IB1 in response to an adjustment start signal ADJ such that a control voltage VC converges to a reference voltage VREF, and ceases the adjustment when the convergence has been achieved. The reference voltage VREF is determined to be a value at an almost middle point in a range of the variable VC in the PLL circuit. The bias current generating circuit has a circuit 23 generating a bias voltage VT and a circuit 24 converting the VT into a current IB2, wherein the temperature characteristic of the bias voltage VT is reverse to that of the control voltage VC under the condition that the frequency of an oscillation signal OCLK is fixed.

公开(公告)号：US06374073B1

公开(公告)日：2002-04-16

申请号：US09882254

申请日：2001-06-18

申请人： Akihiro Ozaki ,  Hideki Ishida

发明人： Akihiro Ozaki ,  Hideki Ishida

IPC分类号： G03G1501

摘要： An image forming machine comprising image bearing means, charging means, exposure means, reversal development means, transfer means, and cleaning means. The transfer means includes a rotationally driven transfer belt, and transfer voltage applicator means for applying a transfer voltage to the back side of the transfer belt. The transfer voltage applicator means applies the transfer voltage to the transfer belt over a predetermined effective transfer width. The face side of the transfer belt is brought into contact with the image bearing means via an image receiving member and directly over a predetermined effective contact width. The effective contact width is larger than an effective charging width and larger than the effective transfer width.

公开(公告)号：US06311139B1

公开(公告)日：2001-10-30

申请号：US09061088

申请日：1998-04-16

申请人： Takao Kuroda ,  Hideki Ishida

发明人： Takao Kuroda ,  Hideki Ishida

IPC分类号： G06F1500

CPC分类号： H01L22/20 ,  H01L2924/0002 ,  H01L2924/00

摘要： The necessary information such as chip area A, number of elements, and defect density D is inputted to calculate element density TD and mean element density TDM. The inverse operation chip area A′ is calculated from the estimation equation: Y=f(A) such as Stapper's equation showing the dependence of the yield on the defect density D and chip area A. Next, for various kinds of integrated circuit devices in a diffusion process, the functional relation g (TD/TDM) which is considered to be most correct is determined from the data of the relationship between the ratio (A′/A) and the ratio (TD/TDM), and from the relational expression g (TD/TDM), the correction factor K is calculated. Finally, the values of the correction factor K and the chip area A are substituted into Y=f(A×K) to calculate the expected yield Y.

摘要翻译： 输入芯片面积A，元件数量和缺陷密度D等必要的信息来计算元件密度TD和平均元件密度TDM。 根据估计方程：Y = f（A）计算反向运算芯片面积A'，例如显示产量对缺陷密度D和芯片面积A的依赖性的Stapper方程。接下来，对于各种集成电路器件 考虑到扩散过程，从比率（A'/ A）和比率（TD / TDM）之间的关系的数据中确定被认为是最正确的功能关系g（TD / TDM），并且从关系 表达式g（TD / TDM），计算校正因子K. 最后，将校正因子K和芯片面积A的值代入Y = f（AxK）来计算预期的产量Y.

公开(公告)号：US06194955B1

公开(公告)日：2001-02-27

申请号：US09283298

申请日：1999-04-01

申请人： Hideki Ishida

发明人： Hideki Ishida

IPC分类号： G05F110

CPC分类号： H03K4/06 ,  H03K17/04106

摘要： A current source switch circuit has at least one transistor forming part of a current source, and one switch for controlling the supply of an electric current from the transistor to a load. A voltage application unit applies a voltage having a value in an operation state as a current source to a transistor forming part of the current source while no electric current is provided from the switch to the load.

摘要翻译： 电流源开关电路具有形成电流源的一部分的至少一个晶体管和用于控制从晶体管到负载的电流的供应的一个开关。 电压施加单元将作为电流源的具有工作状态的值的电压施加到形成电流源的一部分的晶体管，同时没有从开关向负载提供电流。

公开(公告)号：US08274624B2

公开(公告)日：2012-09-25

申请号：US12602604

申请日：2008-05-27

申请人： Takeharu Kitagawa ,  Daisuke Hayashi ,  Hideki Ishida ,  Takeshi Nishibe ,  Nao Murakami

发明人： Takeharu Kitagawa ,  Daisuke Hayashi ,  Hideki Ishida ,  Takeshi Nishibe ,  Nao Murakami

IPC分类号： G02F1/1335

CPC分类号： G02F1/133528 ,  G02B5/3083 ,  G02B27/28 ,  G02F1/133634 ,  G02F2001/133531 ,  G02F2001/133607 ,  G02F2201/50 ,  G02F2202/40 ,  G02F2413/02 ,  G02F2413/07 ,  G02F2413/11 ,  G02F2413/12

摘要： The present invention provides a liquid crystal panel that can provide a neutral display that is free from coloring in every direction. The liquid crystal panel includes a first polarizer 14a, a second polarizer 14b, and a liquid crystal cell 13. The first polarizer 14a is arranged on the visible side of the liquid crystal cell 13 and the second polarizer 14b is arranged on the backlight side of the liquid crystal cell 13. The liquid crystal panel further includes a first retardation layer 11 and a second retardation layer 12. A refractive index ellipsoid of the first retardation layer 11 has a relationship of nx=ny>nz, and a refractive index ellipsoid of the second retardation layer 12 has a relationship of nx>ny≧nz. The first retardation layer 11 and the second retardation layer 12 are arranged between the liquid crystal cell 13 and the second polarizer 14b.

摘要翻译： 本发明提供一种能够提供在各个方向上不着色的中性显示器的液晶面板。 液晶面板包括第一偏振片14a，第二偏振片14b和液晶单元13.第一偏振片14a配置在液晶单元13的可视侧，第二偏振片14b配置在 液晶面板还包括第一延迟层11和第二延迟层12.第一延迟层11的折射率椭圆体的关系为nx = ny> nz，折射率椭圆体的折射率椭圆体 第二延迟层12具有nx>ny≥nz的关系。 第一延迟层11和第二延迟层12布置在液晶单元13和第二偏振器14b之间。

公开(公告)号：US20120236470A1

公开(公告)日：2012-09-20

申请号：US13498500

申请日：2010-09-27

申请人： Hideki Ishida

发明人： Hideki Ishida

IPC分类号： H01G9/048

CPC分类号： H01G9/008 ,  H01G9/048 ,  H01G9/08 ,  H01G9/14

摘要： An electrolytic capacitor comprises a wound body including a wound anode foil with a surface on which a dielectric layer is formed, a solid electrolyte layer formed on a surface of the dielectric layer, a cathode layer formed on a surface of the solid electrolyte layer over the outer circumference of the wound body, a plurality of anode leads electrically connected to the anode foil, and a plurality of cathode leads provided in one-to-one relationship with the anode leads and electrically connected to the cathode layer. The edge surface is a part of the surface of the wound body and crosses the winding axis of the wound body. Each of the cathode leads is electrically connected to an outer circumference of the cathode layer at a position near an anode lead corresponding to this cathode lead.

摘要翻译： 一种电解电容器包括：卷绕体，其包括具有形成有介电层的表面的卷绕的阳极箔，形成在所述电介质层的表面上的固体电解质层，形成在所述固体电解质层的表面上的阴极层， 卷绕体的外周，与阳极箔电连接的多个阳极引线以及与阳极引线一一关系地设置并与阴极层电连接的多个阴极引线。 边缘表面是卷绕体的表面的一部分，并且与卷绕体的卷绕轴线交叉。 每个阴极引线在与该阴极引线相对应的阳极引线附近的位置处电连接到阴极层的外周。

公开(公告)号：US08087556B2

公开(公告)日：2012-01-03

申请号：US11944512

申请日：2007-11-23

申请人： Katsuhiro Oomori ,  Tomoyuki Hoshi ,  Hideki Ishida ,  Masato Sakai ,  Takuya Teranishi ,  Takeshi Taniguchi ,  Takuma Saito ,  Naoki Tadokoro ,  Hideyuki Hashimoto ,  Akira Oono

发明人： Katsuhiro Oomori ,  Tomoyuki Hoshi ,  Hideki Ishida ,  Masato Sakai ,  Takuya Teranishi ,  Takeshi Taniguchi ,  Takuma Saito ,  Naoki Tadokoro ,  Hideyuki Hashimoto ,  Akira Oono

IPC分类号： B25F5/00 ,  A45F5/00

CPC分类号： B25F5/029 ,  B25C7/00 ,  B25F5/02 ,  Y10S224/904

摘要： An electric driver includes a hook portion which is constituted by a deformable hook-like portion and a connecting portion for connecting the hook-like portion to the handle. The hook-like portion is constituted by a base portion connected to the connecting portion and a bent portion continuous to the base portion, and a front end portion continuous to the bent portion and arranged at a position substantially opposed to the base portion. The front end portion and the base portion can be proximate to and remote from each other. The connecting portion holds the hook-like portion in a direction substantially the same as a direction in which the handle extends. The hook-like portion is pivotably held on a first rotating axis center extending in substantially the same direction as the handle.

摘要翻译： 电动驱动器包括由可变形的钩状部分和用于将钩状部分连接到手柄的连接部分构成的钩部。 钩形部分由连接到连接部分的基部和与基部连续的弯曲部分构成，前端部分连接到弯曲部分并且布置在基本上与基部相对的位置。 前端部分和基部部分可以彼此靠近和远离。 连接部分将钩状部分保持在与手柄延伸的方向基本相同的方向上。 钩状部分可枢转地保持在与手柄基本相同的方向上延伸的第一旋转轴中心上。

公开(公告)号：US07659766B2

公开(公告)日：2010-02-09

申请号：US11004807

申请日：2004-12-07

申请人： Hideki Ishida ,  Megumi Oono

发明人： Hideki Ishida ,  Megumi Oono

IPC分类号： H03L5/00

CPC分类号： G05F3/262 ,  H03F3/345 ,  H03F3/4521 ,  H03F2203/45658 ,  H03F2203/45702

摘要： A semiconductor integrated circuit device has a first MIS transistor of a first conductivity type, a second MIS transistor of a second conductivity type, a resistor connected in series between a first power-source line and a second power-source line, and a third MIS transistor of the first conductivity type. The third MIS transistor has a gate connected to a node where the first MIS transistor and the second MIS transistor are connected together, and a drain connected to a connection node where the second MIS transistor and the resistor are connected together.

摘要翻译： 半导体集成电路器件具有第一导电类型的第一MIS晶体管，第二导电类型的第二MIS晶体管，串联连接在第一电源线和第二电源线之间的电阻器，以及第三MIS 第一导电类型的晶体管。 第三MIS晶体管具有连接到第一MIS晶体管和第二MIS晶体管连接在一起的节点的栅极，以及连接到第二MIS晶体管和电阻器连接在一起的连接节点的漏极。