公开(公告)号：US5675172A

公开(公告)日：1997-10-07

申请号：US441707

申请日：1995-05-15

申请人： Masafumi Miyamoto ,  Tatsuya Ishii

发明人： Masafumi Miyamoto ,  Tatsuya Ishii

IPC分类号： H01L29/43 ,  H01L21/265 ,  H01L21/336 ,  H01L21/8238 ,  H01L29/08 ,  H01L29/10 ,  H01L29/423 ,  H01L29/49 ,  H01L29/78 ,  H01L29/76 ,  H01L29/94 ,  H01L31/062

CPC分类号： H01L29/66575 ,  H01L21/823807 ,  H01L29/1033 ,  H01L29/1083 ,  H01L29/66659 ,  H01L29/7802 ,  H01L29/7838 ,  H01L21/2652 ,  H01L21/26586 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/66537

摘要： A MIS device comprising a pair of first doped layers of a second conductivity type forming source/drain regions in a semiconductor base structure of a first conductivity type, and a gate electrode formed in a region between the first doped layers of the second conductivity type on a gate insulating film formed on the semiconductor base structure having a three-layer structure consisting of a second doped layer of the first conductivity type, a third doped layer of the second conductivity type and a fourth doped layer of the first conductivity type having an impurity concentration higher than that of the semiconductor base structure, which are formed in that order in the direction of depth from the surface of a channel region extending between the source/drain regions, the thickness of the third doped layer is determined so that the third doped layer is depleted by the respective built-in potentials of pn junctions formed by the second doped layer and the third doped layer and by the fourth doped layer and the third doped layer, respectively. Even when the MIS device of this structure is miniaturized, the subthreshold swing can be reduced to a value small enough to enable the lowering of the threshold voltage, the electric field intensity in the interface of the gate insulating film is reduced to enhance the carrier mobility and hence the MIS device is suitable for low-voltage operation.

摘要翻译： 一种MIS器件，包括在第一导电类型的半导体基底结构中形成源极/漏极区的第二导电类型的一对第一掺杂层和形成在第二导电类型的第一掺杂层之间的区域中的栅电极 形成在具有由第一导电类型的第二掺杂层，第二导电类型的第三掺杂层和具有杂质的第一导电类型的第四掺杂层组成的三层结构的半导体基底结构上的栅绝缘膜 浓度高于半导体基底结构的浓度，其从在源/漏区之间延伸的沟道区的表面的深度方向依次形成，第三掺杂层的厚度被确定为使得第三掺杂 层被由第二掺杂层和第三掺杂层形成的pn结的相应内置电位以及由fo 第二掺杂层和第三掺杂层。 即使当这种结构的MIS器件小型化时，亚阈值摆幅也可以减小到足以使阈值电压降低的值，从而降低栅极绝缘膜的界面中的电场强度，从而提高载流子迁移率 因此MIS器件适用于低电压工作。