Method and system for error correction in memory devices using irregular error correction code components

    公开(公告)号:US12283972B2

    公开(公告)日:2025-04-22

    申请号:US18341041

    申请日:2023-06-26

    Abstract: Example implementations include a method of optimizing irregular error correction code components in memory devices, a method including obtaining one or more code rate parameters including a payload size parameter, a group size parameter, and a redundancy parameter generating a first number of first code component blocks associated with a first error correction capability, and a second number of code component blocks associated with a second error correction capability aligning the first code component blocks and the second code component blocks to the group size parameter aligning the first code component blocks and the second code component blocks to a code component length constraint, and generating, in accordance with an optimization metric based on the first error correction capability and the second error correction capability, first optimized code components based on the first code component blocks and second optimized code components based on the second code component blocks.

    BIT ERROR RATE ESTIMATION AND CLASSIFICATION IN NAND FLASH MEMORY

    公开(公告)号:US20250124990A1

    公开(公告)日:2025-04-17

    申请号:US18999600

    申请日:2024-12-23

    Abstract: A method for reading data from an SSD, comprising: retrieving data from a target row of memory cells using initial threshold voltages; decoding the data using a first hard decision decoding stage; estimating a bit error rate (BER) of a target row of memory cells based on a distribution of threshold voltages of cells in a memory block containing the target row when the first hard decision decoding stage fails; classifying the BER of the target row based on a first BER threshold (BER-TH1); and executing a first read flow comprising at least one hard decision decoding stage if the BER is less than the BER-TH1, and executing a second read flow similar to the first read flow if the BER is greater than or equal to the BER-TH1, the second read flow skipping a hard decision decoding stage of the first read flow.

    Hard decoding methods in data storage devices

    公开(公告)号:US12210412B2

    公开(公告)日:2025-01-28

    申请号:US18070056

    申请日:2022-11-28

    Abstract: Various implementations described herein relate to systems and methods for decoding data stored in a non-volatile storage device, including determining error candidates and determining whether at least one first error candidate from the error candidates is found based on two of the component codes agreeing on a same error candidate. In addition, whether at least one second error candidate is found based on two of the component codes agreeing on a same error candidate is determined in response to implementing a suggested correction at one of the error candidates. Errors in the data are corrected based on at least one of whether the at least one first error candidate is found or whether the at least one second error candidate is found.

    DEEP NEURAL NETWORK IMPLEMENTATION FOR CONCATENATED CODES

    公开(公告)号:US20240313806A1

    公开(公告)日:2024-09-19

    申请号:US18184916

    申请日:2023-03-16

    CPC classification number: H03M13/2909 H03M13/1105

    Abstract: Systems, methods, non-transitory computer-readable media configured to perform operations associated with a storage medium. One system includes the storage medium and an encoding/decoding (ED) system, the ED system being configured to receive a set of input log-likelihood ratios (LLRs) of a component of the plurality of components, determine an extrinsic estimation function based on a set of features of the set of input LLRs, analyze the extrinsic estimation function to obtain a plurality of extrinsic LLR values, map the plurality of extrinsic LLR values to an input LLR of the set of input LLRs, and output, for each component, a plurality of updated LLR values based on the mapping.

    System and method for high reliability fast raid soft decoding for NAND flash memories

    公开(公告)号:US11258466B1

    公开(公告)日:2022-02-22

    申请号:US16819025

    申请日:2020-03-13

    Abstract: A flash memory system may include a flash memory and a circuit for decoding a result of a read operation on the flash memory using a first codeword. The circuit may be configured to generate first soft information of the first codeword. The circuit may be further configured to generate second soft information of a second codeword. The circuit may be configured to generate third soft information based on the first soft information and the second soft information. The circuit may be configured to decode the result of the read operation on the flash memory using the third soft information.

    Codeword concatenation for correcting errors in data storage devices

    公开(公告)号:US11258464B1

    公开(公告)日:2022-02-22

    申请号:US16844725

    申请日:2020-04-09

    Abstract: Various implementations described herein relate to systems and methods for encoding and decoding data having input payload stored in a non-volatile storage device, including encoding the input payload by concatenating a plurality of short codewords to generate a plurality of encoded short codewords, and decoding the plurality of encoded short codewords to obtain the data, where each of the plurality of short codewords corresponding to a portion of the input payload.

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