Edge seal configurations for a lower electrode assembly

    公开(公告)号:US10892197B2

    公开(公告)日:2021-01-12

    申请号:US16115627

    申请日:2018-08-29

    Abstract: A lower electrode assembly configured to support a semiconductor substrate in a plasma processing chamber includes a base plate, an upper plate above the base plate, and a mounting groove surrounding a bond layer located between the base plate and the upper plate. An edge seal including a compressible ring is mounted in the mounting groove such that the compressible ring is axially compressed between the upper plate and the base plate. At least one gas passage is in fluid communication with an annular space between the compressible ring and an inner wall of the mounting groove. The at least gas one passage extends through the base plate and includes a plurality of outlets in fluid communication with the annular space. In some examples, a backing seal may be located between the edge seal and an inner wall of the mounting groove.

    Method of determining thermal stability of a substrate support assembly

    公开(公告)号:US09716022B2

    公开(公告)日:2017-07-25

    申请号:US14109020

    申请日:2013-12-17

    CPC classification number: G05B19/418 H01L21/67103 H01L21/67248

    Abstract: A method of determining thermal stability of an upper surface of a substrate support assembly comprises recording time resolved pre-process temperature data of the substrate before performing a plasma processing process while powering an array of thermal control elements to achieve a desired spatial and temporal temperature of the upper surface. A substrate is processed while powering the array of thermal control elements to achieve a desired spatial and temporal temperature of the upper surface of the assembly, and time resolved post-process temperature data of the assembly is recorded after processing the substrate. The post-process temperature data is recorded while powering the thermal control elements to achieve a desired spatial and temporal temperature of the upper surface. The post-process temperature data is compared to the pre-process temperature data to determine whether the data is within a desired tolerance range.

    MULTI-PLANE HEATER FOR SEMICONDUCTOR SUBSTRATE SUPPORT

    公开(公告)号:US20170167790A1

    公开(公告)日:2017-06-15

    申请号:US14966198

    申请日:2015-12-11

    Abstract: A semiconductor substrate support for supporting a semiconductor substrate in a plasma processing chamber includes a multi-plane heater such as a heater array comprising thermal control elements operable to tune a spatial temperature profile on the semiconductor substrate. The multi-plane heater includes at least one pair of vertically offset heating elements connected in series or parallel to control heating output in a heating zone on the substrate support. The thermal control elements can be powered by two or more power supply lines and two or more power return lines wherein each power supply line is connected to at least two of the heater zones and each power return line is connected to at least two of the heater zones.

    Method and Apparatus for Chuck Thermal Calibration
    25.
    发明申请
    Method and Apparatus for Chuck Thermal Calibration 审中-公开
    卡盘热校准方法与装置

    公开(公告)号:US20130235506A1

    公开(公告)日:2013-09-12

    申请号:US13868044

    申请日:2013-04-22

    CPC classification number: H01L21/6833 H01L21/67248

    Abstract: A chuck includes a first material layer having an upper surface upon which a wafer is supported. The upper surface includes portions that physically contact the wafer and portions that form gaps between the upper surface and the wafer. The chuck also includes a second material layer defined to support the first material layer. The second material layer is formed of a thermally conductive material and includes a first number of channels. The chuck also includes a second number of channels defined to direct a gas to portions of the upper surface that form gaps between the upper surface and the wafer. The chuck is characterized by a thermal calibration curve that represents a thermal interface between the upper surface and the wafer, heat transfer through the first material layer to the second material layer, and heat transfer through the second material layer to the first number of channels.

    Abstract translation: 卡盘包括具有上表面的第一材料层,晶片被支撑在该上表面上。 上表面包括物理接触晶片的部分和在上表面和晶片之间形成间隙的部分。 卡盘还包括限定为支撑第一材料层的第二材料层。 第二材料层由导热材料形成并且包括第一数量的通道。 卡盘还包括限定为将气体引导到在上表面和晶片之间形成间隙的上表面的部分的通道的第二数量。 卡盘的特征在于热校准曲线,其表示上表面和晶片之间的热界面,通过第一材料层的热传递到第二材料层,以及通过第二材料层的热传递到第一数量的通道。

Patent Agency Ranking