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    Decoding System and Method for Electronic Non-Volatile Computer Storage Apparatus
    21.
    发明申请
    Decoding System and Method for Electronic Non-Volatile Computer Storage Apparatus 有权
    电子非易失性计算机存储设备的解码系统和方法

    公开(公告)号：US20150227403A1

    公开(公告)日：2015-08-13

    申请号：US14200659

    申请日：2014-03-07

    Applicant: LSI CORPORATION

    Inventor： Fan Zhang ,  Yu Chin Fabian Lim ,  Shu Li

    IPC: G06F11/07

    CPC classification number: G11C11/5642 ,  G06F11/1008 ,  G06F11/1012 ,  H03M13/1105 ,  H03M13/3723 ,  H03M13/373 ,  H03M13/451 ,  H03M13/6325

    Abstract: Methods are systems for calculating log-likelihood ratios for a decoder utilized in an electronic non-volatile computer storage apparatus are disclosed. A log-likelihood ratio handler is configured to provide an input log-likelihood ratio to the decoder, wherein the input log-likelihood ratio is one of: a uniform input log-likelihood ratio for all bits calculated based on an estimated raw bit error rate for a particular data unit, or a bit-based input log-likelihood ratio for each bit calculated based on a confidence value for a cell containing said each bit. The decoder of the electronic non-volatile computer storage apparatus is configured to decode encoded data at least partially based on the input log-likelihood ratio from the log-likelihood ratio handler.

    Abstract translation: 方法是公开了用于计算在电子非易失性计算机存储装置中使用的解码器的对数似然比的系统。 对数似然比处理器被配置为向解码器提供输入对数似然比，其中输入对数似然比是以下之一：基于估计的原始误码率计算的所有比特的均匀输入对数似然比 或针对包含所述每个位的单元的置信度值计算的每个位的基于位的输入对数似然比。 电子非易失性计算机存储装置的解码器被配置为至少部分地基于来自对数似然比处理器的输入对数似然比来解码编码数据。

    Encoding and decoding in flash memories using convolutional-type low-density parity check codes
    22.
    发明授权
    Encoding and decoding in flash memories using convolutional-type low-density parity check codes 有权
    使用卷积型低密度奇偶校验码对闪存进行编码和解码

    公开(公告)号：US09106264B2

    公开(公告)日：2015-08-11

    申请号：US13755676

    申请日：2013-01-31

    Applicant: LSI Corporation

    Inventor： Abdel Hakim S. Alhussien ,  Erich F. Haratsch ,  Zongwang Li ,  Fan Zhang

    IPC: G11C16/04 ,  H03M13/23 ,  G06F11/10 ,  H03M13/11

    CPC classification number: H03M13/23 ,  G06F11/1072 ,  H03M13/1154 ,  H03M13/6325

    Abstract: Methods and apparatus are provided for encoding and decoding in flash memories using convolutional-type low parity density check codes. A plurality of bits to be stored on a flash memory device are encoded using a convolutional-type low density parity check code, such as a spatially coupled low density parity check code. The encoded pages or portions thereof can be decoded independently of other pages. In one embodiment, an encoded page is decoded jointly with one or more additional pages in the same wordline or a different wordline.

    Abstract translation: 提供了使用卷积型低奇偶校验密码校验码来对闪速存储器进行编码和解码的方法和装置。 使用诸如空间耦合的低密度奇偶校验码的卷积型低密度奇偶校验码对要存储在闪速存储器件上的多个比特进行编码。 编码的页面或其部分可以独立于其他页面被解码。 在一个实施例中，编码页面与同一字线或不同字线中的一个或多个附加页面联合解码。

    Systems and methods for large sector dynamic format insertion
    26.
    发明授权
    Systems and methods for large sector dynamic format insertion 有权
    大型动态格式插入的系统和方法

    公开(公告)号：US08976475B1

    公开(公告)日：2015-03-10

    申请号：US14080946

    申请日：2013-11-15

    Applicant: LSI Corporation

    Inventor： Shu Li ,  Fan Zhang ,  Jun Xiao

    IPC: G11B5/09

    CPC classification number: G06F11/1469 ,  G06F17/30424 ,  G06F17/30581 ,  G11B5/09 ,  G11B20/1217 ,  G11B2020/1287

    Abstract: Systems and method relating generally to data processing, and more particularly to systems and methods for segmenting a data set and recovering the segmented data set. In one case, a system is disclosed that includes: a data transfer preparation circuit, a transfer characteristic determination circuit, and a a format insertion circuit. The data transfer preparation circuit is operable to receive a user data set and to generate an output data set based upon the user data set; the transfer characteristic determination circuit is operable to determine a distance between a first servo data wedge on a storage medium and a second servo data wedge on the storage medium; and the format insertion circuit is operable to dynamically augment the output data set with formatting information at a location selected based at least in part on the distance between the first servo data wedge and the second servo data wedge.

    Abstract translation: 一般涉及数据处理的系统和方法，更具体地涉及用于分割数据集并恢复分段数据集的系统和方法。 在一种情况下，公开了一种系统，包括：数据传输准备电路，传输特性确定电路和格式插入电路。 数据传输准备电路可操作以接收用户数据集并且基于用户数据集生成输出数据集; 传输特性确定电路可操作以确定存储介质上的第一伺服数据楔与存储介质上的第二伺服数据楔之间的距离; 并且所述格式插入电路可操作以使用至少部分地基于所述第一伺服数据楔和所述第二伺服数据楔之间的距离所选择的位置的格式化信息动态地增大所述输出数据集。

    Threshold acquisition and adaption in NAND flash memory
    29.
    发明授权
    Threshold acquisition and adaption in NAND flash memory 有权
    NAND闪存中的阈值采集和适配

    公开(公告)号：US08942037B2

    公开(公告)日：2015-01-27

    申请号：US13664583

    申请日：2012-10-31

    Applicant: LSI Corporation

    Inventor： Haitao Xia ,  Fan Zhang ,  Ming Jin ,  Shaohua Yang

    IPC: G11C11/34

    CPC classification number: G11C16/06 ,  G11C16/34 ,  G11C16/349

    Abstract: A method, apparatus, and controller for acquiring and tracking at least one threshold voltage of at least one cell of at least one flash chip. The method can include acquiring the at least one threshold voltage of a particular cell of the at least one flash cell. The method can further include performing at least one threshold voltage adjustment iteration.

    Abstract translation: 一种用于获取和跟踪至少一个闪存芯片的至少一个单元的至少一个阈值电压的方法，装置和控制器。 该方法可以包括获取至少一个闪存单元的特定单元的至少一个阈值电压。 该方法还可以包括执行至少一个阈值电压调整迭代。

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