公开(公告)号：US06531932B1

公开(公告)日：2003-03-11

申请号：US09894210

申请日：2001-06-27

申请人： Anand Govind ,  Farshad Ghahghahi ,  Aritharan Thurairajaratnam

发明人： Anand Govind ,  Farshad Ghahghahi ,  Aritharan Thurairajaratnam

IPC分类号： H01P308

CPC分类号： H01P3/084 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73253 ,  H01L2924/15311 ,  H01P3/088

摘要： A method for fabricating a microstrip package to optimize signal trace impedance control is disclosed. The method includes patterning a plurality of signal traces on a multilayer substrate, and patterning a plurality of guard traces on the multilayer substrate, that are interspersed alternately among the signal traces to provide noise shielding between the signal traces. In a further embodiment, the traces are patterned on the substrate with a width that is adjusted at different locations based on the presence the guard traces to enable the package to meet a particular impedance requirement.

摘要翻译： 公开了一种用于制造微带封装以优化信号迹线阻抗控制的方法。 该方法包括在多层衬底上图形化多条信号迹线，以及对多层衬底上的多条保护迹线进行构图，其中交替地在信号迹线之间散布以提供信号迹线之间的噪声屏蔽。 在另一个实施例中，迹线在衬底上被图案化，其宽度基于保护迹线的存在而被调整到不同的位置，以使封装能够满足特定的阻抗要求。

公开(公告)号：US06407462B1

公开(公告)日：2002-06-18

申请号：US09753000

申请日：2000-12-30

申请人： Nikon Banouvong ,  Farshad Ghahghahi

发明人： Nikon Banouvong ,  Farshad Ghahghahi

IPC分类号： H01L2328

CPC分类号： H01L24/10 ,  H01L23/49827 ,  H01L23/49838 ,  H01L24/13 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/16 ,  H01L2924/01005 ,  H01L2924/01033 ,  H01L2924/014 ,  H01L2924/14 ,  H01L2924/15173 ,  H01L2924/15311 ,  H01L2924/00

摘要： According to the present invention, a first plurality of solder bumps are arranged the active surface of an integrated circuit die in the form of a grid comprising a plurality of rows and a plurality of columns, where the plurality of rows are parallel to two opposing edges of the active surface and the plurality of columns are perpendicular to the plurality of rows. The plurality of columns are separated by a distance D. Each of the solder bumps in every other row is separated from an adjacent solder bump in that row by a distance 2D such that the each of these solder bumps is disposed along a first group of the plurality of columns. Each of the solder bumps in the remaining rows, is separated from an adjacent solder bump in that row by the distance 2D such that the solder bumps in the remaining rows are disposed along a second group of the plurality of columns. Each column within the second group of columns is adjacent to, and in between, two of the columns within the first group of columns. In other words, the solder bump pads are staggered.

摘要翻译： 根据本发明，第一多个焊料凸块以包括多行和多列的格栅形式布置在集成电路管芯的有源表面上，其中多个行平行于两个相对边缘 并且所述多个列垂直于所述多个行。 多个列分开距离D.每隔一行的每个焊料凸块与该行中的相邻焊料凸块分开距离2D，使得这些焊料凸块中的每一个沿着第一组 多列。 剩余行中的每个焊料凸块与该行中的相邻焊料凸块分开距离2D，使得剩余行中的焊料凸块沿多个列的第二组布置。 第二组列中的每列与第一组列中的两列之间相邻，并位于两列之间。 换句话说，焊料凸块是交错的。

公开(公告)号：US6114761A

公开(公告)日：2000-09-05

申请号：US009580

申请日：1998-01-20

申请人： Atila Mertol ,  Zeki Z. Celik ,  Farshad Ghahghahi ,  Zafer S. Kutlu

发明人： Atila Mertol ,  Zeki Z. Celik ,  Farshad Ghahghahi ,  Zafer S. Kutlu

IPC分类号： H01L23/367 ,  H01L23/34 ,  H01L23/10 ,  H01L23/48

CPC分类号： H01L23/367 ,  H01L2224/16 ,  H01L2224/73253 ,  H01L2924/00014 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16195

摘要： A thermally-enhanced flip chip integrated circuit (IC) package has a package substrate to which an IC die is bonded. A thermally-conductive heatspreader, having planar dimensions larger than the IC die, is thermally bonded at or near its center to an upper surface of the IC die. A plurality of cooling extensions are formed that protrude from a lower surface (the surface closest to the package substrate) of the heatspreader so as to create passageways through which cooling air may flow. In one embodiment, the cooling extensions are parallel fins that protrude transversely from the lower surface of the heatspreader, thereby forming U-shaped channels. In another embodiment, the cooling extensions are an array of fin pins that protrude transversely from the lower surface of the heatspreader.

摘要翻译： 热增强型倒装芯片集成电路（IC）封装具有与IC芯片接合的封装基板。 具有比IC芯片大的平面尺寸的导热散热器在其中心处或其附近热粘合到IC芯片的上表面。 形成从散热器的下表面（最接近封装基板的表面）突出的多个冷却延伸部，以便形成冷却空气可流过的通道。 在一个实施例中，冷却延伸部是从散热器的下表面横向突出的平行翅片，从而形成U形通道。 在另一个实施例中，冷却延伸部是从散热器的下表面横向突出的翅片销的阵列。