公开(公告)号：US07350029B2

公开(公告)日：2008-03-25

申请号：US11054889

申请日：2005-02-10

申请人： Eric Jason Fluhr ,  Bradly George Frey ,  John Barry Griswell, Jr. ,  Hung Qui Le ,  Cathy May ,  Francis Patrick O'Connell ,  Edward John Silha ,  Albert Thomas Williams

发明人： Eric Jason Fluhr ,  Bradly George Frey ,  John Barry Griswell, Jr. ,  Hung Qui Le ,  Cathy May ,  Francis Patrick O'Connell ,  Edward John Silha ,  Albert Thomas Williams

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0862 ,  G06F2212/6028

摘要： A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.

摘要翻译： 在微处理器中预取数据的方法包括基于包括当前并发数据流的数量和与并发数据流相关联的数据消耗速率的预取因子来识别与进程相关联的数据流并确定与数据流相关联的深度。 数据预取请求被分配与数据流以反映确定的数据流的深度。 分配数据预取请求可以包括为当前被引用的高速缓存行分配多个高速缓存行的预取请求，其中高速缓存行的数量等于所确定的深度。 该方法可以响应于确定与数据流相关联的深度，配置预取硬件以反映所识别的数据流的确定的深度。 由处理器执行的指令中的预取控制位控制预取硬件配置。

公开(公告)号：US07039760B2

公开(公告)日：2006-05-02

申请号：US10425443

申请日：2003-04-28

申请人： Ravi Kumar Arimilli ,  John David McCalpin ,  Francis Patrick O'Connell ,  William John Starke

发明人： Ravi Kumar Arimilli ,  John David McCalpin ,  Francis Patrick O'Connell ,  William John Starke

IPC分类号： G06F12/00

CPC分类号： G06F12/123 ,  G06F12/127

摘要： A method and apparatus for managing cache lines in a data processing system. A special purpose register is employed in which this register may be manipulated by user code and operating system code to set preferences, such as a level 2 cache management policy preference for an application thread. These preferences may be dynamically set and an arbitration mechanism is employed to best satisfy preferences of multiple threads with a single aggregate preference. Members are represented using a least recently used tree. The least recent used tree has a set of nodes forming a path to member cache lines in a hierarchical structure. A state of a selected node is selectively biased within the set of nodes in the least recently used tree. At least one node on a level below the selected node is eliminated from being selected in managing the cache lines. In this manner, members can be biased against or for selection as victims when replacing cache lines in a cache memory.

摘要翻译： 一种用于在数据处理系统中管理高速缓存行的方法和装置。 使用专用寄存器，其中该寄存器可以由用户代码和操作系统代码来操作以设置优先级，诸如针对应用程序线程的2级缓存管理策略偏好。 这些偏好可以被动态设置，并且使用仲裁机制来最好地满足具有单个聚合偏好的多个线程的偏好。 会员使用最近最少使用的树来表示。 最近使用的树具有一组以层次结构形成到成员高速缓存行的路径的节点。 所选节点的状态在最近最少使用的树中的节点集合内被有选择地偏置。 在选择的节点以下的级别上的至少一个节点在管理高速缓存行时被排除。 以这种方式，当替换高速缓冲存储器中的高速缓存行时，成员可以偏向于或被选择为受害者。

公开(公告)号：US06535962B1

公开(公告)日：2003-03-18

申请号：US09435860

申请日：1999-11-08

申请人： Michael John Mayfield ,  Francis Patrick O'Connell ,  David Scott Ray

发明人： Michael John Mayfield ,  Francis Patrick O'Connell ,  David Scott Ray

IPC分类号： G06F1200

CPC分类号： G06F12/0862 ,  G06F12/0897 ,  G06F2212/6026 ,  G06F2212/6028

摘要： A data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache and a third level cache and a system memory. Prefetching of cache lines is performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches is performed over a private prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor.

摘要翻译： 数据处理系统包括具有第一级高速缓存和预取引擎的处理器。 耦合到处理器的是二级缓存和第三级缓存和系统存储器。 通过预取引擎对高速缓存行的预取执行到第一，第二和第三级高速缓存中的每一个。 从预取引擎到第二和第三级高速缓存的预取请求通过专用预取请求总线执行，该专用预取请求总线与将数据从各种高速缓存级别传送到处理器的总线系统分开。

公开(公告)号：US06460115B1

公开(公告)日：2002-10-01

申请号：US09435865

申请日：1999-11-08

申请人： James Allan Kahle ,  Michael John Mayfield ,  Francis Patrick O'Connell ,  David Scott Ray ,  Edward John Silha ,  Joel Tendler

发明人： James Allan Kahle ,  Michael John Mayfield ,  Francis Patrick O'Connell ,  David Scott Ray ,  Edward John Silha ,  Joel Tendler

IPC分类号： G06F1300

CPC分类号： G06F9/3802 ,  G06F9/30047 ,  G06F9/383 ,  G06F12/0862 ,  G06F12/0897 ,  G06F2212/6028

摘要： A data processing system and method for prefetching data in a multi-level code subsystem. The data processing system includes a processor having a first level cache and a prefetch engine. Coupled to the processor are a second level cache, and a third level cache and a system memory. Prefetching of cache lines is concurrently performed into each of the first, second, and third level caches by the prefetch engine. Prefetch requests from the prefetch engine to the second and third level caches are performed over a private or dedicated prefetch request bus, which is separate from the bus system that transfers data from the various cache levels to the processor. A software instruction or hint may be used to accelerate the prefetch process by overriding the normal functionality of the hardware prefetch engine.

摘要翻译： 一种用于在多级代码子系统中预取数据的数据处理系统和方法。 数据处理系统包括具有第一级高速缓存和预取引擎的处理器。 耦合到处理器的是第二级缓存，以及第三级缓存和系统存储器。 通过预取引擎将高速缓存行预取同时执行到第一，第二和第三级高速缓存中的每一个。 从预取引擎到第二级和第三级高速缓存的预取请求通过私有或专用预取请求总线执行，该专用或专用预取请求总线与将数据从各种高速缓存级别传送到处理器的总线系统分开。 软件指令或提示可用于通过覆盖硬件预取引擎的正常功能来加速预取过程。