公开(公告)号：US07350029B2

公开(公告)日：2008-03-25

申请号：US11054889

申请日：2005-02-10

申请人： Eric Jason Fluhr ,  Bradly George Frey ,  John Barry Griswell, Jr. ,  Hung Qui Le ,  Cathy May ,  Francis Patrick O'Connell ,  Edward John Silha ,  Albert Thomas Williams

发明人： Eric Jason Fluhr ,  Bradly George Frey ,  John Barry Griswell, Jr. ,  Hung Qui Le ,  Cathy May ,  Francis Patrick O'Connell ,  Edward John Silha ,  Albert Thomas Williams

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0862 ,  G06F2212/6028

摘要： A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.

摘要翻译： 在微处理器中预取数据的方法包括基于包括当前并发数据流的数量和与并发数据流相关联的数据消耗速率的预取因子来识别与进程相关联的数据流并确定与数据流相关联的深度。 数据预取请求被分配与数据流以反映确定的数据流的深度。 分配数据预取请求可以包括为当前被引用的高速缓存行分配多个高速缓存行的预取请求，其中高速缓存行的数量等于所确定的深度。 该方法可以响应于确定与数据流相关联的深度，配置预取硬件以反映所识别的数据流的确定的深度。 由处理器执行的指令中的预取控制位控制预取硬件配置。

公开(公告)号：US07904661B2

公开(公告)日：2011-03-08

申请号：US11953637

申请日：2007-12-10

申请人： Eric Jason Fluhr ,  Bradly George Frey ,  John Barry Griswell, Jr. ,  Hung Qui Le ,  Cathy May ,  Francis Patrick O'Connell ,  Edward John Silha ,  Albert Thomas Williams

发明人： Eric Jason Fluhr ,  Bradly George Frey ,  John Barry Griswell, Jr. ,  Hung Qui Le ,  Cathy May ,  Francis Patrick O'Connell ,  Edward John Silha ,  Albert Thomas Williams

IPC分类号： G06F12/00 ,  G06F13/00

CPC分类号： G06F12/0862 ,  G06F2212/6028

摘要： A method of prefetching data in a microprocessor includes identifying a data stream associated with a process and determining a depth associated with the data stream based upon prefetch factors including the number of currently concurrent data streams and data consumption rates associated with the concurrent data streams. Data prefetch requests are allocated with the data stream to reflect the determined depth of the data stream. Allocating data prefetch requests may include allocating prefetch requests for a number of cache lines away from the cache line currently being referenced, wherein the number of cache lines is equal to the determined depth. The method may include, responsive to determining the depth associated with a data stream, configuring prefetch hardware to reflect the determined depth for the identified data stream. Prefetch control bits in an instruction executed by the processor control the prefetch hardware configuration.

摘要翻译： 在微处理器中预取数据的方法包括基于包括当前并发数据流的数量和与并发数据流相关联的数据消耗速率的预取因子来识别与进程相关联的数据流并确定与数据流相关联的深度。 数据预取请求被分配与数据流以反映确定的数据流的深度。 分配数据预取请求可以包括为当前被引用的高速缓存行分配多个高速缓存行的预取请求，其中高速缓存行的数量等于所确定的深度。 该方法可以响应于确定与数据流相关联的深度，配置预取硬件以反映所识别的数据流的确定的深度。 由处理器执行的指令中的预取控制位控制预取硬件配置。

公开(公告)号：US08140759B2

公开(公告)日：2012-03-20

申请号：US12424716

申请日：2009-04-16

申请人： Bradly George Frey ,  Guy Lynn Guthrie ,  Cathy May ,  Ramakrishnan Rajamony ,  Balaram Sinharoy ,  William John Starke ,  Peter Kenneth Szwed

发明人： Bradly George Frey ,  Guy Lynn Guthrie ,  Cathy May ,  Ramakrishnan Rajamony ,  Balaram Sinharoy ,  William John Starke ,  Peter Kenneth Szwed

IPC分类号： G06F13/00

CPC分类号： G06F12/0862 ,  G06F12/0811 ,  G06F12/0817 ,  G06F2212/6028

摘要： A system and method for specifying an access hint for prefetching only a subsection of cache block data, for more efficient system interconnect usage by the processor core. A processing unit receives a data cache block touch (DCBT) instruction containing an access hint and identifying a specific size portion of data to be prefetched. Both the access hint and a value corresponding to an amount of data to be prefetched are contained in separate subfields of the DCBT instruction. In response to detecting that the code point is set to a specific value, only the specific size of data identified in a sub-field of the DCBT and addressed in the DCBT instruction is prefetched into an entry in the lower level cache.

摘要翻译： 用于指定用于仅预取高速缓存块数据的子部分的访问提示的系统和方法，用于处理器核心的更有效的系统互连使用。 处理单元接收包含访问提示的数据高速缓存块触摸（DCBT）指令，并且识别要预取的数据的特定大小部分。 访问提示和对应于要预取的数据量的值都包含在DCBT指令的单独子字段中。 响应于检测到代码点被设置为特定值，仅在DCBT指令的DCBT的子字段中标识的数据的特定大小被预取到低级缓存中的条目中。

公开(公告)号：US20100268886A1

公开(公告)日：2010-10-21

申请号：US12424716

申请日：2009-04-16

申请人： Bradly George Frey ,  Guy Lynn Guthrie ,  Cathy May ,  Ramakrishnan Rajamony ,  Balaram Sinharoy ,  William John Starke ,  Peter Kenneth Szwed

发明人： Bradly George Frey ,  Guy Lynn Guthrie ,  Cathy May ,  Ramakrishnan Rajamony ,  Balaram Sinharoy ,  William John Starke ,  Peter Kenneth Szwed

IPC分类号： G06F12/08 ,  G06F12/00

CPC分类号： G06F12/0862 ,  G06F12/0811 ,  G06F12/0817 ,  G06F2212/6028

摘要： A system and method for specifying an access hint for prefetching only a subsection of cache block data, for more efficient system interconnect usage by the processor core. A processing unit receives a data cache block touch (DCBT) instruction containing an access hint and identifying a specific size portion of data to be prefetched. Both the access hint and a value corresponding to an amount of data to be prefetched are contained in separate subfields of the DCBT instruction. In response to detecting that the code point is set to a specific value, only the specific size of data identified in a sub-field of the DCBT and addressed in the DCBT instruction is prefetched into an entry in the lower level cache.

摘要翻译： 用于指定用于仅预取高速缓存块数据的子部分的访问提示的系统和方法，用于处理器核心的更有效的系统互连使用。 处理单元接收包含访问提示的数据高速缓存块触摸（DCBT）指令，并且识别要预取的数据的特定大小部分。 访问提示和对应于要预取的数据量的值都包含在DCBT指令的单独子字段中。 响应于检测到代码点被设置为特定值，仅在DCBT指令的DCBT的子字段中标识的数据的特定大小被预取到低级缓存中的条目中。

公开(公告)号：US20090193233A1

公开(公告)日：2009-07-30

申请号：US12043747

申请日：2008-03-06

申请人： Ronald N. Kalla ,  Cathy May ,  Balaram Sinharoy ,  Edward John Silha ,  Shih-Hsiung S. Tung

发明人： Ronald N. Kalla ,  Cathy May ,  Balaram Sinharoy ,  Edward John Silha ,  Shih-Hsiung S. Tung

IPC分类号： G06F9/318

CPC分类号： G06F9/3861 ,  G06F9/30189 ,  G06F9/383 ,  G06F9/3842

摘要： A method and processor for avoiding check stops in speculative accesses. An execution unit, e.g., load/store unit, may be coupled to a queue configured to store instructions. A register, coupled to the execution unit, may be configured to store a value corresponding to an address in physical memory. When the processor is operating in real mode, the execution unit may retrieve the value stored in the register. Upon the execution unit receiving a speculative instruction, e.g., speculative load instruction, from the queue, a determination may be made as to whether the address of the speculative instruction is at or below the retrieved value. If the address of the speculative instruction is at or below this value, then the execution unit may safely speculatively execute this instruction while avoiding a check stop since all the addresses at or below this value are known to exist in physical memory.

摘要翻译： 一种用于避免投机访问中检查停止的方法和处理器。 执行单元，例如加载/存储单元，可以被耦合到被配置为存储指令的队列。 耦合到执行单元的寄存器可被配置为存储对应于物理存储器中的地址的值。 当处理器以实模式运行时，执行单元可以检索存储在寄存器中的值。 在执行单元从队列接收诸如推测性加载指令的推测性指令之后，可以确定推测指令的地址是否在检索值以下。 如果推测指令的地址处于或低于该值，则执行单元可以安全地推测性地执行该指令，同时避免检查停止，因为已知存在于该物理存储器中的所有地址或低于该值的地址。

公开(公告)号：US07370177B2

公开(公告)日：2008-05-06

申请号：US10424527

申请日：2003-04-25

申请人： Ronald N. Kalla ,  Cathy May ,  Balaram Sinharoy ,  Edward John Silha ,  Shih-Hsiung S. Tung

发明人： Ronald N. Kalla ,  Cathy May ,  Balaram Sinharoy ,  Edward John Silha ,  Shih-Hsiung S. Tung

IPC分类号： G06F9/30

CPC分类号： G06F9/3861 ,  G06F9/30189 ,  G06F9/383 ,  G06F9/3842

摘要： A method and processor for avoiding check stops in speculative accesses. An execution unit, e.g., load/store unit, may be coupled to a queue configured to store instructions. A register, coupled to the execution unit, may be configured to store a value corresponding to an address in physical memory. When the processor is operating in real mode, the execution unit may retrieve the value stored in the register. Upon the execution unit receiving a speculative instruction, e.g., speculative load instruction, from the queue, a determination may be made as to whether the address of the speculative instruction is at or below the retrieved value. If the address of the speculative instruction is at or below this value, then the execution unit may safely speculatively execute this instruction while avoiding a check stop since all the addresses at or below this value are known to exist in physical memory.

摘要翻译： 一种用于避免投机访问中检查停止的方法和处理器。 执行单元，例如加载/存储单元，可以被耦合到被配置为存储指令的队列。 耦合到执行单元的寄存器可被配置为存储对应于物理存储器中的地址的值。 当处理器以实模式运行时，执行单元可以检索存储在寄存器中的值。 在执行单元从队列接收诸如推测性加载指令的推测性指令之后，可以确定推测指令的地址是否在检索值以下。 如果推测指令的地址处于或低于该值，则执行单元可以安全地推测性地执行该指令，同时避免检查停止，因为已知存在于该物理存储器中的所有地址或低于该值的地址。

公开(公告)号：US07822942B2

公开(公告)日：2010-10-26

申请号：US12054538

申请日：2008-03-25

申请人： Michael J. Corrigan ,  Paul LuVerne Godtland ,  Joaquin Hinojosa ,  Cathy May ,  Naresh Nayar ,  Edward John Silha

发明人： Michael J. Corrigan ,  Paul LuVerne Godtland ,  Joaquin Hinojosa ,  Cathy May ,  Naresh Nayar ,  Edward John Silha

IPC分类号： G06F13/00

CPC分类号： G06F12/1036 ,  G06F12/126 ,  G06F2212/1016 ,  G06F2212/683

摘要： An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries are invalidated.

摘要翻译： 一种装置和方法选择性地使地址转换高速缓存中的条目无效，而不是使所有或几乎所有条目无效。 在地址转换高速缓存中的每个条目中提供一个或多个翻译模式位。 可以根据用于创建高速缓存条目的寻址模式来设置这些转换模式位。 在指令中定义一个或多个“提示位”，该指令允许根据翻译模式位的值来指定在无效操作期间选择性地保留地址转换高速缓存中的哪些条目。 在替代方案中，可以定义多个指令以保留具有指定寻址模式的地址转换高速缓存中的条目。 以这种方式，使用更多的智能来识别地址转换高速缓存中的一些条目在任务或分区切换之后可能是有效的，并且因此可以被保留，而其他条目无效。

公开(公告)号：US07949859B2

公开(公告)日：2011-05-24

申请号：US12043747

申请日：2008-03-06

申请人： Ronald N. Kalla ,  Cathy May ,  Balaram Sinharoy ,  Edward John Silha ,  Shih-Hsiung S. Tung

发明人： Ronald N. Kalla ,  Cathy May ,  Balaram Sinharoy ,  Edward John Silha ,  Shih-Hsiung S. Tung

IPC分类号： G06F9/00

CPC分类号： G06F9/3861 ,  G06F9/30189 ,  G06F9/383 ,  G06F9/3842

摘要： A method and processor for avoiding check stops in speculative accesses. An execution unit, e.g., load/store unit, may be coupled to a queue configured to store instructions. A register, coupled to the execution unit, may be configured to store a value corresponding to an address in physical memory. When the processor is operating in real mode, the execution unit may retrieve the value stored in the register. Upon the execution unit receiving a speculative instruction, e.g., speculative load instruction, from the queue, a determination may be made as to whether the address of the speculative instruction is at or below the retrieved value. If the address of the speculative instruction is at or below this value, then the execution unit may safely speculatively execute this instruction while avoiding a check stop since all the addresses at or below this value are known to exist in physical memory.

摘要翻译： 一种用于避免投机访问中检查停止的方法和处理器。 执行单元，例如加载/存储单元，可以被耦合到被配置为存储指令的队列。 耦合到执行单元的寄存器可被配置为存储对应于物理存储器中的地址的值。 当处理器以实模式运行时，执行单元可以检索存储在寄存器中的值。 在执行单元从队列接收诸如推测性加载指令的推测性指令之后，可以确定推测指令的地址是否在检索值以下。 如果推测指令的地址处于或低于该值，则执行单元可以安全地推测性地执行该指令，同时避免检查停止，因为已知存在于该物理存储器中的所有地址或低于该值的地址。

公开(公告)号：US20080168254A1

公开(公告)日：2008-07-10

申请号：US12054538

申请日：2008-03-25

申请人： Michael J. Corrigan ,  Paul LuVerne Godtland ,  Joaquin Hinojosa ,  Cathy May ,  Naresh Nayar ,  Edward John Silha

发明人： Michael J. Corrigan ,  Paul LuVerne Godtland ,  Joaquin Hinojosa ,  Cathy May ,  Naresh Nayar ,  Edward John Silha

IPC分类号： G06F9/34

CPC分类号： G06F12/1036 ,  G06F12/126 ,  G06F2212/1016 ,  G06F2212/683

摘要： An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries are invalidated.

摘要翻译： 一种装置和方法选择性地使地址转换高速缓存中的条目无效，而不是使所有或几乎所有条目无效。 在地址转换高速缓存中的每个条目中提供一个或多个翻译模式位。 可以根据用于创建高速缓存条目的寻址模式来设置这些转换模式位。 在指令中定义一个或多个“提示位”，该指令允许根据翻译模式位的值来指定在无效操作期间选择性地保留地址转换高速缓存中的哪些条目。 在替代方案中，可以定义多个指令以保留具有指定寻址模式的地址转换高速缓存中的条目。 以这种方式，使用更多的智能来识别地址转换高速缓存中的一些条目在任务或分区切换之后可能是有效的，并且因此可以被保留，而其他条目无效。

公开(公告)号：US07389400B2

公开(公告)日：2008-06-17

申请号：US11304136

申请日：2005-12-15

申请人： Michael J. Corrigan ,  Paul LuVerne Godtland ,  Joaquin Hinojosa ,  Cathy May ,  Naresh Nayar ,  Edward John Silha

发明人： Michael J. Corrigan ,  Paul LuVerne Godtland ,  Joaquin Hinojosa ,  Cathy May ,  Naresh Nayar ,  Edward John Silha

IPC分类号： G06F12/00

CPC分类号： G06F12/1036 ,  G06F12/126 ,  G06F2212/1016 ,  G06F2212/683

摘要： An apparatus and method selectively invalidate entries in an address translation cache instead of invalidating all, or nearly all, entries. One or more translation mode bits are provided in each entry in the address translation cache. These translation mode bits may be set according to the addressing mode used to create the cache entry. One or more “hint bits” are defined in an instruction that allow specifying which of the entries in the address translation cache are selectively preserved during an invalidation operation according to the value(s) of the translation mode bit(s). In the alternative, multiple instructions may be defined to preserve entries in the address translation cache that have specified addressing modes. In this manner, more intelligence is used to recognize that some entries in the address translation cache may be valid after a task or partition switch, and may therefore be retained, while other entries in the address translation cache are invalidated.

摘要翻译： 一种装置和方法选择性地使地址转换高速缓存中的条目无效，而不是使所有或几乎所有条目无效。 在地址转换高速缓存中的每个条目中提供一个或多个翻译模式位。 可以根据用于创建高速缓存条目的寻址模式来设置这些转换模式位。 在指令中定义一个或多个“提示位”，该指令允许根据翻译模式位的值来指定在无效操作期间选择性地保留地址转换高速缓存中的哪些条目。 在替代方案中，可以定义多个指令以保留具有指定寻址模式的地址转换高速缓存中的条目。 以这种方式，使用更多的智能来识别地址转换高速缓存中的一些条目在任务或分区切换之后可能是有效的，并且因此可以被保留，而地址转换高速缓存中的其他条目是无效的。