公开(公告)号：US20220122665A1

公开(公告)日：2022-04-21

申请号：US17542562

申请日：2021-12-06

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Vishal Sarin

IPC: G11C15/04 ,  G11C16/10 ,  G11C16/04 ,  H01L27/00 ,  G11C13/06

Abstract: Memory devices might include a plurality of memory cell pairs each configured to be programmed to store a digit of data; and control circuitry configured to cause the memory device to compare the stored digit of data of each memory cell pair to a received digit of data, determine whether a match condition or a no-match condition is indicated between the stored digit of data of each memory cell pair and the received digit of data, and deem a match condition to be met between the received digit of data and the stored digits of data of the plurality of memory cell pairs in response to a match condition being determined for a majority of memory cell pairs of the plurality of memory cell pairs.

公开(公告)号：US10712960B2

公开(公告)日：2020-07-14

申请号：US16166231

申请日：2018-10-22

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge

IPC: G06F3/06 ,  G11C11/00 ,  G11C15/04 ,  G06F11/22 ,  G06F11/10 ,  G11C16/04

Abstract: Memory devices, and methods of operating similar memory devices, include an array of memory cells comprising a plurality of access lines each configured for biasing control gates of a respective plurality of memory cells of the array of memory cells, wherein the respective plurality of memory cells for one access line of the plurality of access lines is mutually exclusive from the respective plurality of memory cells for each remaining access line of the plurality of access lines, and a controller having a plurality of selectively-enabled operating modes and configured to selectively operate the memory device using two or more concurrently enabled operating modes of the plurality of selectively-enabled operating modes for access of the array of memory cells, with each of the enabled operating modes of the two of more concurrently enabled operating modes utilizing an assigned respective portion of the array of memory cells.

公开(公告)号：US20190341115A1

公开(公告)日：2019-11-07

申请号：US16515134

申请日：2019-07-18

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis

IPC: G11C16/26 ,  G11C16/08 ,  G11C7/10 ,  G06N3/04 ,  G06N3/063 ,  G11C16/04

Abstract: Memory having an array of memory cells and a controller for access of the array of memory cells that is configured to generate a data value indicative of a level of a property sensed from a data line while applying potentials to control gates of memory cells of more than one string of series-connected memory cells connected to that data line.

公开(公告)号：US10261713B2

公开(公告)日：2019-04-16

申请号：US15945316

申请日：2018-04-04

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge

IPC: G06F3/06 ,  G11C11/00 ,  G11C15/04 ,  G06F11/22 ,  G06F11/10 ,  G11C16/04

Abstract: Memory devices, and methods of operating similar memory devices, include an array of memory cells comprising a plurality of access lines each configured for biasing control gates of a respective plurality of memory cells of the array of memory cells, wherein the respective plurality of memory cells for one access line of the plurality of access lines is mutually exclusive from the respective plurality of memory cells for each remaining access line of the plurality of access lines, and a controller having a plurality of selectively-enabled operating modes and configured to selectively operate the memory device using two or more concurrently enabled operating modes of the plurality of selectively-enabled operating modes for access of the array of memory cells, with each of the enabled operating modes of the two of more concurrently enabled operating modes utilizing an assigned respective portion of the array of memory cells.

公开(公告)号：US10068653B2

公开(公告)日：2018-09-04

申请号：US15241496

申请日：2016-08-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis

IPC: G11C16/10 ,  G11C16/26 ,  G06N3/04 ,  G06N3/063 ,  G11C16/04 ,  G11C7/10 ,  G11C16/08

Abstract: Methods of operating memory include generating a data value indicative of a level of a property sensed from a data line while applying potentials to control gates of memory cells of more than one string of series-connected memory cells connected to that data line. Methods of operating memory further include generating data values indicative of levels of a property sensed from data lines while applying potentials to control gates of memory cells of strings of series-connected memory cells connected to those data lines, performing a logical operation on a set of data values comprising those data values, and determining a potential to be applied to control gates of different memory cells of those strings of series-connected memory cells in response to an output of the logical operation on the set of data values.

公开(公告)号：US09875799B1

公开(公告)日：2018-01-23

申请号：US14991007

申请日：2016-01-08

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Vishal Sarin

IPC: G11C11/34 ,  G11C15/04 ,  G11C16/10 ,  G11C16/04

CPC classification number: G11C15/046 ,  G11C16/0483 ,  G11C16/10 ,  G11C29/52

Abstract: Memories having a plurality of cell pairs, where each cell pair of the plurality of cell pairs is programmed to store a same bit of data corresponding to a particular bit position of a pattern to be searched in a memory are useful in mitigating match errors, such as in a CAM (Content Addressable Memory) memory device.

公开(公告)号：US20160232978A1

公开(公告)日：2016-08-11

申请号：US15132455

申请日：2016-04-19

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Luca De Santis ,  Tommaso Vali ,  Kenneth J. Eldredge ,  Frankie F. Roohparvar

IPC: G11C16/10 ,  G11C16/04

CPC classification number: G11C16/10 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3418

Abstract: Methods for operating memory cells include applying a respective minterm, comprising a plurality of variables, to control gates of series strings of memory cells, each series string programmed as a plurality of pairs of complementary memory cells such that certain ones of the plurality of variables are enabled, and logically combining each of the minterms into a logic function output. Memories include a plurality of memory cells configured in series strings of memory cells, wherein each series string of memory cells is configured to provide a minterm comprising a plurality of variables, each variable enabled responsive to a state of an associated, respective memory cell.

Abstract translation: 用于操作存储器单元的方法包括应用包括多个变量的相应最小值来控制存储器单元的串联串的栅极，每个串行串被编程为多对互补存储器单元，使得多个变量中的某些变量是 启用并逻辑地将每个minterms组合成逻辑功能输出。 存储器包括配置成串联的存储器单元串的多个存储器单元，其中存储器单元的每个串联串被配置为提供包括多个变量的最小值，每个变量响应于相关联的相应存储单元的状态而启用。

公开(公告)号：US09105330B1

公开(公告)日：2015-08-11

申请号：US13864659

申请日：2013-04-17

Applicant: Micron Technology, Inc.

Inventor： Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca de Santis ,  Tommaso Vali

IPC: G11C15/00

CPC classification number: G11C16/28 ,  G11C15/00 ,  G11C15/046 ,  G11C16/0483

Abstract: Memory devices and methods are disclosed. One such method compares input data to stored data in a memory device and includes applying a first weight factor to a first string of memory cells coupled to a data line, where a first bit of the stored data is stored in the first string of memory cells; applying a second weight factor to a second string of memory cells coupled to the data line, where a second bit of the stored data is stored in the second string of memory cells; comparing a first bit of input data to the first bit of the stored data while the first weight factor is applied to the first string of memory cells; and comparing a second bit of the input data to the second bit of the stored data while the second weight factor is applied to the second string of memory cells.

Abstract translation: 公开了存储器件和方法。 一种这样的方法将输入数据与存储器件中的存储数据进行比较，并且包括将第一加权因子应用于耦合到数据线的存储器单元的第一串，其中存储的数据的第一位被存储在第一存储单元串中 ; 将第二加权因子应用于耦合到所述数据线的第二存储单元串，其中所述存储数据的第二位存储在所述第二存储单元串中; 将第一加权因子应用于第一串存储器单元时，将第一比特的输入数据与存储数据的第一比较; 以及将所述输入数据的第二位与存储的数据的第二位进行比较，同时将所述第二权重因子应用于所述第二存储单元串。

公开(公告)号：US11074982B2

公开(公告)日：2021-07-27

申请号：US16989191

申请日：2020-08-10

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Tommaso Vali ,  Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis

IPC: G11C16/26 ,  G06N3/04 ,  G06N3/063 ,  G11C7/10 ,  G11C16/08 ,  G11C16/04

Abstract: Memory having an array of memory cells and configured to store a first value representative of a characteristic sensed from a first data line, store a second value representative of the characteristic sensed from a second data line, perform an operation on the first value and the data value at a first logic circuitry, and perform an operation on an output of the first logic circuitry and a threshold data value at a second logic circuitry.

公开(公告)号：US10770152B2

公开(公告)日：2020-09-08

申请号：US16180137

申请日：2018-11-05

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kenneth J. Eldredge ,  Frankie F. Roohparvar ,  Luca De Santis ,  Tommaso Vali

IPC: G11C16/28 ,  G11C15/00 ,  G11C15/04 ,  G11C16/04

Abstract: Methods of operating a memory device include comparing input data to data stored in strings of series-connected memory cells coupled to a data line, generating a respective resistance in series with each string of series-connected memory cells while comparing the plurality of digits of input data to the stored data, comparing a representation of a level of current in the data line to a reference, deeming the input data to match the stored data in response to the representation of the level of current in the data line being less than the reference, and deeming the input data to not match the stored data in response to the representation of the level of current in the data line being greater than the reference.