MEMORY ARRAY WITH MULTIPLEXED DIGIT LINES
    21.
    发明申请

    公开(公告)号:US20200327926A1

    公开(公告)日:2020-10-15

    申请号:US16379222

    申请日:2019-04-09

    Abstract: Methods, systems, and devices for a memory device with multiplexed digit lines are described. In some cases, a memory cell of the memory device may include a storage component and a selection component that includes two transistors. A first transistor may be coupled with a word line and a second transistor may be coupled with a select line to selectively couple the memory cell with a digit line. The selection component, in conjunction with a digit line multiplexing component, may support a sense component common to a set of digit lines. In some cases, the digit line of the set may be coupled with the sense component during a read operation, while the remaining digit lines of the set are isolated from the sense component.

    APPARATUSES AND METHODS FOR CALIBRATING SENSE AMPLIFIERS IN A SEMICONDUCTOR MEMORY

    公开(公告)号:US20190035436A1

    公开(公告)日:2019-01-31

    申请号:US15662059

    申请日:2017-07-27

    Abstract: Apparatuses and methods for calibrating sense at in a semiconductor memory are disclosed. An example apparatus includes an amplifier circuit and a calibration circuit. The amplifier circuit is configured to be coupled to a supply voltage and a reference voltage, and when activated the amplifier circuit is configured to provide an output signal at an output that is complementary to an input signal provided to an input. When activated by a calibration signal, the calibration circuit is configured to provide a calibration voltage to the of the amplifier circuit, wherein the calibration voltage is in equilibration voltage between the supply voltage and the reference voltage provided to the amplifier circuit.

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