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公开(公告)号：US20240242758A1
公开(公告)日：2024-07-18
申请号：US18421741
申请日：2024-01-24
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Stefan Frederik Schippers
IPC: G11C11/4096 , G11C11/408 , G11C11/4091 , H10B12/00 , G11C11/56
CPC classification number: G11C11/4096 , G11C11/4085 , G11C11/4091 , H10B12/30 , H10B12/50 , G11C11/4087 , G11C11/565
Abstract: Methods, systems, and devices for a memory device with multiplexed digit lines are described. In some cases, a memory cell of the memory device may include a storage component and a selection component that includes two transistors. A first transistor may be coupled with a word line and a second transistor may be coupled with a select line to selectively couple the memory cell with a digit line. The selection component, in conjunction with a digit line multiplexing component, may support a sense component common to a set of digit lines. In some cases, the digit line of the set may be coupled with the sense component during a read operation, while the remaining digit lines of the set are isolated from the sense component.
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公开(公告)号：US20200294573A1
公开(公告)日：2020-09-17
申请号：US16854239
申请日：2020-04-21
Applicant: Micron Technology, Inc.
Inventor： Daniele Vimercati , Stefan Frederik Schippers , Xinwei Guo
IPC: G11C11/4091 , G11C11/408 , H03F3/45 , G11C11/22
Abstract: Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, a memory apparatus may include a differential amplifier having a first input node configured to be coupled with a memory cell and having an output node configured to be coupled with a sense component. In some examples, the memory apparatus may also include a capacitor having a first node coupled with the first input node, and a first switching component configured to selectively couple a second node of the capacitor with the output node. The differential amplifier may configured such that a current at the output node is proportional to a difference between a voltage at the first input node of the differential amplifier and a voltage at the second input node of the differential amplifier.
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公开(公告)号：US20230097079A1
公开(公告)日：2023-03-30
申请号：US16976411
申请日：2020-05-25
Applicant: Micron Technology, Inc.
Inventor： Paolo Fantini , Corrado Villa , Stefan Frederik Schippers , Efrem Bolandrina
Abstract: The present disclosure provides a memory device and accessing/de-selecting methods thereof. The memory device comprises a memory layer including a vertical three-dimensional (3D) memory array of memory cells formed therein, wherein a memory cell is accessed through a word line and a digit line orthogonal to each other, and the digit line is in a form of conductive pillar extending vertically; a pillar selection layer formed under the memory layer and having thin film transistors (TFTs) formed therein for accessing memory cells; and a peripheral circuit layer formed under the pillar selection layer and having a sense amplifier and a decoding circuitry for word lines and bit lines, wherein a TFT is configured for each pillar.
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公开(公告)号：US20220366983A1
公开(公告)日：2022-11-17
申请号：US17597816
申请日：2020-12-09
Applicant: Micron Technology, Inc.
Inventor： Paolo Fantini , Corrado Villa , Stefan Frederik Schippers , Lorenzo Fratin
Abstract: The present disclosure provides a memory apparatus and a method for accessing a 3D vertical memory array. The 3D vertical memory array comprises word lines organized in planes separated from each other by insulating material, bit lines perpendicular to the word line planes, memory cells coupled between a respective word line and a respective bit line. The apparatus also comprises a controller configured to select multiple word lines, select multiple bit lines, and simultaneously access multiple memory cells, with each memory cell at a crossing of a selected word line and a selected bit line. The method comprises selecting a multiple word lines, selecting multiple bit lines and simultaneously accessing multiple memory cells, with each memory cell at a crossing of a selected word line of the selected multiple word lines and a selected bit line of the selected multiple bit lines. A method of manufacturing a 3D vertical memory array is also described.
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公开(公告)号：US20210407581A1
公开(公告)日：2021-12-30
申请号：US17370488
申请日：2021-07-08
Applicant: Micron Technology, Inc.
Inventor： Ferdinando Bedeschi , Stefan Frederik Schippers
IPC: G11C11/4096 , G11C11/4091 , G11C11/408 , H01L27/108
Abstract: Methods, systems, and devices for a memory device with multiplexed digit lines are described. In some cases, a memory cell of the memory device may include a storage component and a selection component that includes two transistors. A first transistor may be coupled with a word line and a second transistor may be coupled with a select line to selectively couple the memory cell with a digit line. The selection component, in conjunction with a digit line multiplexing component, may support a sense component common to a set of digit lines. In some cases, the digit line of the set may be coupled with the sense component during a read operation, while the remaining digit lines of the set are isolated from the sense component.
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Patent Agency Ranking
公开(公告)号：US10339983B1
公开(公告)日：2019-07-02
申请号：US15857704
申请日：2017-12-29
Applicant: Micron Technology, Inc.
Inventor： Emanuele Confalonieri , Stefano Ratti , Gary G. Lazarowics , Stefan Frederik Schippers , Stefano Claudio Roseghini , Angelo Clemente Scardilla
CPC classification number: G11C7/04 , G01K3/005 , G06F3/0616 , G06F3/064 , G06F3/0679 , G11C13/0033 , G11C16/26 , G11C16/3431
Abstract: Apparatuses, methods, and devices that can be utilized to provide temperature-based memory operations are described. One or more apparatuses can include a memory device and a controller coupled to the memory device and configured to: determine an operating temperature of the apparatus, determine one of a plurality of designated open blocks of the memory device to write data based on the operating temperature of the apparatus and a size of the data, and write the data in the determined one of the plurality of designated blocks of the memory device.
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公开(公告)号：US10529389B2
公开(公告)日：2020-01-07
申请号：US16389666
申请日：2019-04-19
Applicant: MICRON TECHNOLOGY, INC.
Inventor： Stefan Frederik Schippers
IPC: G11C7/02 , G11C7/08 , G11C14/00 , G11C11/4091 , G11C29/02
Abstract: Apparatuses and methods for calibrating sense amplifiers in a semiconductor memory are disclosed. An example apparatus includes an amplifier circuit and a calibration circuit. The amplifier circuit is configured to be coupled to a supply voltage and a reference voltage, and when activated the amplifier circuit is configured to provide an output signal at an output that is complementary to an input signal provided to an input. When activated by a calibration signal, the calibration circuit is configured to provide a calibration voltage to the output of the amplifier circuit, wherein the calibration voltage is an equilibration voltage between the supply voltage and the reference voltage provided to the amplifier circuit.
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公开(公告)号：US20190385663A1
公开(公告)日：2019-12-19
申请号：US16453208
申请日：2019-06-26
Applicant: Micron Technology, Inc.
Inventor： Daniele Vimercati , Stefan Frederik Schippers , Xinwei Guo
IPC: G11C11/4091 , G11C11/408 , H03F3/45 , G11C11/22
Abstract: Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, a memory apparatus may include a differential amplifier having a first input node configured to be coupled with a memory cell and having an output node configured to be coupled with a sense component. In some examples, the memory apparatus may also include a capacitor having a first node coupled with the first input node, and a first switching component configured to selectively couple a second node of the capacitor with the output node. The differential amplifier may configured such that a current at the output node is proportional to a difference between a voltage at the first input node of the differential amplifier and a voltage at the second input node of the differential amplifier.
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公开(公告)号：US10388361B1
公开(公告)日：2019-08-20
申请号：US15920171
申请日：2018-03-13
Applicant: Micron Technology, Inc.
Inventor： Daniele Vimercati , Stefan Frederik Schippers , Xinwei Guo
IPC: G11C11/24 , G11C11/4091 , G11C11/408 , H03F3/45 , G11C11/22
Abstract: Methods, systems, and devices for differential amplifier schemes for sensing memory cells are described. In one example, a memory apparatus may include a differential amplifier having a first input node configured to be coupled with a memory cell and having an output node configured to be coupled with a sense component. In some examples, the memory apparatus may also include a capacitor having a first node coupled with the first input node, and a first switching component configured to selectively couple a second node of the capacitor with the output node. The differential amplifier may configured such that a current at the output node is proportional to a difference between a voltage at the first input node of the differential amplifier and a voltage at the second input node of the differential amplifier.
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公开(公告)号：US20190206452A1
公开(公告)日：2019-07-04
申请号：US15857704
申请日：2017-12-29
Applicant: Micron Technology, Inc.
Inventor： Emanuele Confalonieri , Stefano Ratti , Gary G. Lazarowics , Stefan Frederik Schippers , Stefano Claudio Roseghini , Angelo Clemente Scardilla
CPC classification number: G11C7/04 , G01K3/005 , G06F3/0616 , G06F3/064 , G06F3/0679 , G11C13/0033 , G11C16/26 , G11C16/3431
Abstract: Apparatuses, methods, and devices that can be utilized to provide temperature-based memory operations are described. One or more apparatuses can include a memory device and a controller coupled to the memory device and configured to: determine an operating temperature of the apparatus, determine one of a plurality of designated open blocks of the memory device to write data based on the operating temperature of the apparatus and a size of the data, and write the data in the determined one of the plurality of designated blocks of the memory device.
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