公开(公告)号：US12040024B2

公开(公告)日：2024-07-16

申请号：US17493475

申请日：2021-10-04

Applicant: MACRONIX International Co., Ltd.

Inventor： Ya-Jui Lee ,  Kuan-Fu Chen

IPC: G11C16/16

CPC classification number: G11C16/16

Abstract: A flash memory and an erase method thereof are provided. The flash memory includes at least a memory array and a memory control circuit. The memory control circuit biases plural word lines, a common source line and a global bit line included in the memory array to erase plural memory cells in the flash memory. The method comprises grouping the plural word lines into plural word line groups according to erase depths corresponding to each word line; generating an erase voltage and plural multiple-step word line erase voltages; applying the erase voltage from at least one of the common source line and the global bit line; and during a period when the erase voltage is applied, the plural multiple-step word line erase voltages is respectively applied to the plural word line groups, wherein the plural multiple-step word line erase voltages is one-by-one corresponding to the plural word line groups.

公开(公告)号：US20240221835A1

公开(公告)日：2024-07-04

申请号：US18090499

申请日：2022-12-29

Applicant: MACRONIX International Co., Ltd.

Inventor： Ya-Jui Lee ,  Kuan-Fu Chen

IPC: G11C16/08 ,  G11C16/28

CPC classification number: G11C16/08 ,  G11C16/28

Abstract: A memory device and programming method thereof are provided. A memory cell array includes a first dummy word line set, plural word lines and a second dummy word line set in sequence. The method includes: grouping the word lines into word line groups; generating at least one pass bias set having plural pass biases that are respectively corresponding to each word line group; selecting one word line for programming, and determining that the selected word line belongs to a specific word line group; and according to a programming sequence, applying a corresponding pass bias in the plural pass biases of the at least one pass bias set to at least one dummy word line in one of the first and the second dummy word line sets, wherein the corresponding pass bias corresponds to the specific word line group.

公开(公告)号：US11101004B1

公开(公告)日：2021-08-24

申请号：US16908328

申请日：2020-06-22

Applicant: MACRONIX International Co., Ltd.

Inventor： Ya-Jui Lee

IPC: G11C16/04 ,  G11C16/34 ,  G11C16/26 ,  G11C16/30 ,  G11C16/08 ,  G11C16/10 ,  G11C16/24

Abstract: A memory device and a reading method thereof are provided. During a second reading period, a second bit line voltage is provided to a bit line having a read finished memory cell. Thus, a voltage difference between a bit line voltage and a pass voltage of memory cells on unselected word lines is reduced. A data value stored in the memory cells on a selected word line is determined according to whether the memory cells on the selected word line enter a preset state during a first reading period and the second reading period.

公开(公告)号：US10665303B1

公开(公告)日：2020-05-26

申请号：US16409470

申请日：2019-05-10

Applicant: Macronix International Co., Ltd.

Inventor： Ya-Jui Lee ,  Kuan-Fu Chen

IPC: G11C16/16 ,  G11C16/34 ,  G11C16/04 ,  G11C16/26 ,  G11C16/10

Abstract: Methods, systems and apparatus for effectively erasing blocks with few programmed pages are provided. In one aspect, a system includes a memory and a controller coupled to the memory. The memory includes blocks each having pages. The controller is configured to determine whether a threshold page with a particular page number in a block of the memory is programmed, to erase the block according to a normal erase action in response to determining that the threshold page is programmed, and to erase the block according to a particular erasing action that is configured to erase the block deeper than the normal erase action in response to determining that the threshold page is not programmed. The particular erasing action can include pre-programming the block before erasing the block, decreasing an erase verify voltage before erasing the block, or adding one or more erasing pulses with a new erasing voltage.

公开(公告)号：US09613702B1

公开(公告)日：2017-04-04

申请号：US14986124

申请日：2015-12-31

Applicant: MACRONIX International Co., Ltd.

Inventor： Ya-Jui Lee ,  Kuan-Fu Chen

IPC: G11C11/34 ,  G11C16/08 ,  G11C11/418 ,  G11C16/24 ,  G11C16/04

CPC classification number: G11C16/08 ,  G11C5/05 ,  G11C5/063 ,  G11C11/418 ,  G11C16/0408 ,  G11C16/0483 ,  G11C16/24 ,  H01L27/11519 ,  H01L27/11524

Abstract: A memory device including multiple word lines, multiple bit lines and a memory cell array is provided. The word lines intersect the bit lines, and an included angle between the word lines and the bit lines is not a right angle. The memory cell array includes multiple memory cells respectively disposed at the intersections of the word lines and the bit lines. Each row of the memory cells is electrically connected to one of the word lines, and each column of the memory cells is electrically connected to one of the bit lines.