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公开(公告)号：US20250104773A1
公开(公告)日：2025-03-27
申请号：US18474619
申请日：2023-09-26
Applicant: MACRONIX International Co., Ltd.
Inventor： Chen Wang , Ya-Jui Lee
Abstract: A memory device and an operating method for the memory device are provided. The memory device includes a memory array and a control circuit. The memory array includes memory blocks. Each of the memory blocks is, for example a three-dimensional NAND flash memory block. The memory device provides a storage media with high-performance and high-capacity. The control circuit provides a first erasing voltage to perform a first erasing operation on target memory cell strings of a selected memory block in the memory blocks, performs a programming operation on the target memory cell strings after the first erasing operation, and provides a second erasing voltage to perform a second erasing operation on at least one part of memory cells of each of the target memory cell strings after the programming operation. The second erasing voltage is lower than the first erasing voltage.
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2.发明授权公开(公告)号：US11056172B1
公开(公告)日：2021-07-06
申请号：US16860349
申请日：2020-04-28
Applicant: MACRONIX International Co., Ltd.
Inventor： Che-Ping Chen , Ya-Jui Lee , Shin-Jang Shen , Yih-Shan Yang
IPC: G11C7/22 , G11C11/4076 , G11C11/4074 , G11C11/4099 , G11C11/4094 , G11C11/408 , G11C16/04 , G11C16/32 , G11C16/34 , G11C16/26 , G11C16/06
Abstract: A flash memory and an operation method thereof are provided. The flash memory includes a plurality of memory cell strings and a pass voltage generator. Each of the memory cell strings includes a plurality of memory cells. The pass voltage generator is configured to provide a pass voltage to a plurality of word lines of a plurality of unselected memory cells of a selected memory string. During a reading operation, the pass voltage generator raises the pass voltage from a first voltage at a first time point, and raises the pass voltage to a second voltage at a second time point. The second voltage is lower than a target voltage times a preset ratio The first time point is earlier than a start time point of a bit line voltage received by the selected memory cell, and the second time point occurs at the start time point of the bit line voltage.
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公开(公告)号：US10714197B1
公开(公告)日：2020-07-14
申请号：US16388300
申请日：2019-04-18
Applicant: MACRONIX International Co., Ltd.
Inventor： Ya-Jui Lee , Kuan-Fu Chen
Abstract: A memory device and a program verification method thereof are provided. The write verification method includes: reading a previous page to obtain first read data, writing input data to a current page, reading the previous page or the current page to obtain second read data, and analyzing at least one of the first read data and the second read data to determine whether to back up at least one of the first read data and the input data to a redundant block of the memory device.
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4.发明授权公开(公告)号：US10026490B2
公开(公告)日：2018-07-17
申请号：US15288785
申请日：2016-10-07
Applicant: MACRONIX International Co., Ltd.
Inventor： Ya-Jui Lee , Kuan-Fu Chen
CPC classification number: G11C16/3459 , G11C16/0483 , G11C16/08 , G11C16/10 , G11C16/12 , G11C16/26
Abstract: A memory device and a programming method thereof are provided, and the programming method of the memory device includes following steps. A memory cell grouping procedure is performed to divide a plurality of memory cells into a plurality of groups. After the memory cell grouping procedure is performed, a programming procedure is performed, and the programming procedure includes following steps. A first programming pulse, a second programming pulse and a verification pulse are provided to a word line. A first group is programmed by the first programming pulse, and a second group is programmed by the second programming pulse. Whether the first group and the second group respectively pass a verification operation is determined by the verification pulse.
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公开(公告)号：US09779820B1
公开(公告)日：2017-10-03
申请号：US15440889
申请日：2017-02-23
Applicant: MACRONIX International Co., Ltd.
Inventor： Ya-Jui Lee , Kuan-Fu Chen
CPC classification number: G11C16/10 , G11C16/0483 , G11C16/08 , G11C16/24 , G11C16/32 , G11C16/3427
Abstract: A non-volatile memory and a programming method thereof are provided. The programming method for the non-volatile memory includes: setting at least one first isolation cell between a first side cell and at least one first pass cell of an inhibited memory string; cutting off the at least one first isolation cell and providing a pre-boosting voltage to a word line of the first side cell and at a first time point; turning on the at least one first isolation cell at a second time point for transporting the pre-boosting potential to channels of the at least one first pass cell and a primary cell at a second time period; and providing a boosting voltage to word lines of the at least one first pass cell during a boosting time period.
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Patent Agency Ranking
公开(公告)号：US20250104778A1
公开(公告)日：2025-03-27
申请号：US18475247
申请日：2023-09-27
Applicant: MACRONIX International Co., Ltd.
Inventor： Che-Ping Chen , Ya-Jui Lee
Abstract: An operation method of a memory device including the following operations is provided. Applying a read voltage to a selected page of a plurality of programmed memory pages. Applying a first pass voltage to unselected pages of the plurality of programmed memory pages. Applying a second pass voltage to at least one unprogrammed memory page, wherein the first pass voltage is larger than the second pass voltage. A memory system including a 3D NAND flash memory with high capacity and high performance is also provided.
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公开(公告)号：US11145373B1
公开(公告)日：2021-10-12
申请号：US16882071
申请日：2020-05-22
Applicant: MACRONIX International Co., Ltd.
Inventor： Ya-Jui Lee , Kuan-Fu Chen
Abstract: A method for programming a memory device and a memory system are provided, wherein the method for programming the memory device includes steps below. First, a program command is proposed. Second, a width of a pulse about to provide to strings of memory cells of the memory device is determined according to a temperature data of the memory device. Then, the pulse is provided to the strings of memory cells to start doing a program operation. The width of the pulse becomes narrower as a temperature of the memory device is raised.
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公开(公告)号：US11056205B1
公开(公告)日：2021-07-06
申请号：US16908626
申请日：2020-06-22
Applicant: MACRONIX International Co., Ltd.
Inventor： Ya-Jui Lee , Kuan-Fu Chen
Abstract: A memory device and a write method thereof are provided. A control circuit performs a first write operation and a first write verification operation on a plurality of memory cells of a non-volatile memory, and after the plurality of memory cells pass the first write verification operation, the control circuit performs a second write verification operation on target memory cells corresponding to at least one target threshold voltage in the plurality of memory cells, and when a failure bit count of the target memory cells is not less than a preset number of bits, the control circuit performs a second write operation and a third write verification operation on the plurality of memory cells.
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公开(公告)号：US10460808B2
公开(公告)日：2019-10-29
申请号：US15793045
申请日：2017-10-25
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Ya-Jui Lee , Kuan-Fu Chen
Abstract: Provided is an operation method for a memory device. The memory device includes a memory array having a plurality of word lines and a plurality of bit lines. The operation method for the memory device includes: applying a program voltage to at least one selected word line of the word lines; and during a high level of the program voltage, based on respective locations of a plurality of selected bit line, which are to be written into data 0, on the word lines, applying different plurality of bit line voltages to the selected bit line which are to be written into data 0.
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10.发明申请公开(公告)号：US20190122735A1
公开(公告)日：2019-04-25
申请号：US15793045
申请日：2017-10-25
Applicant: MACRONIX INTERNATIONAL CO., LTD.
Inventor： Ya-Jui Lee , Kuan-Fu Chen
CPC classification number: G11C16/08 , G11C11/5628 , G11C16/10 , G11C16/12 , G11C16/14 , G11C16/24 , G11C16/32
Abstract: Provided is an operation method for a memory device. The memory device includes a memory array having a plurality of word lines and a plurality of bit lines. The operation method for the memory device includes: applying a program voltage to at least one selected word line of the word lines; and during a high level of the program voltage, based on respective locations of a plurality of selected bit line, which are to be written into data 0, on the word lines, applying different plurality of bit line voltages to the selected bit line which are to be written into data 0.
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