Abstract:
A system including a phase comparator to compare a first signal and a second signal to generate a phase error signal, and a controller to generate an adjusted phase error signal from the phase error signal in response to an amplitude of at least one of the first signal and the second signal.
Abstract:
An improved Received Signal Strength Indicator (RSSI) circuit and method is provided herein for quickly and accurately detecting the strength of a received signal. The circuit described herein provides a more accurate RSSI signal, while consuming less power and die area, by utilizing digital rather than analog summing.
Abstract:
A crystal oscillator circuit which does not produce runt pulses when the oscillator is turned on or off. The circuit includes a crystal oscillator, an integrator which integrates the energy in a plurality of pulses, a threshold circuit which is active when the output of the integrator reaches a pre-specified threshold and gating circuits which gate the output of the crystal oscillator to the output terminal only when the threshold circuit has reached the specified threshold.
Abstract:
A frequency synthesizer apparatus is disclosed which combines a digital multiplier in the count down and phase comparison section with an oscillator entirely contained on an integrated circuit. Inclusion of the digital multiplier allows simultaneous realization of high loop bandwidth and fast tuning speed. The large loop bandwidth facilitates use of a totally integrated oscillator, which was heretofore not useable because of inferior phase noise characteristics. An integrated filter further enhances loop bandwidth while maintaining stability. Synchronizing the modulus switching of a multi-modulus prescaler with the multiplier coefficient minimizes spurious responses in the synthesized output.
Abstract:
A digital receiver samples data from an amplitude modulated subcarrier at a rate less than twice the subcarrier's maximum frequency by sampling at known phase points. Sampling at known phase points is achieved by generating a sampling clock from a signal phase locked to and transmitted with the modulated data subcarrier.