Digital received signal strength indicator (RSSI) circuit and method for detecting the strength of a received signal
    22.
    发明授权
    Digital received signal strength indicator (RSSI) circuit and method for detecting the strength of a received signal 有权
    数字接收信号强度指示器(RSSI)电路及检测接收信号强度的方法

    公开(公告)号:US07660567B1

    公开(公告)日:2010-02-09

    申请号:US11531886

    申请日:2006-09-14

    CPC classification number: H04B17/318

    Abstract: An improved Received Signal Strength Indicator (RSSI) circuit and method is provided herein for quickly and accurately detecting the strength of a received signal. The circuit described herein provides a more accurate RSSI signal, while consuming less power and die area, by utilizing digital rather than analog summing.

    Abstract translation: 本文提供了一种改进的接收信号强度指示(RSSI)电路和方法,用于快速准确地检测接收信号的强度。 本文描述的电路通过利用数字而不是模拟求和来提供更准确的RSSI信号,同时消耗更少的功率和管芯面积。

    Circuit and method to eliminate startup and shutoff runt pulses from crystal oscillators
    23.
    发明授权
    Circuit and method to eliminate startup and shutoff runt pulses from crystal oscillators 失效
    消除晶体振荡器启动和关断欠压脉冲的电路和方法

    公开(公告)号:US07057434B1

    公开(公告)日:2006-06-06

    申请号:US10834950

    申请日:2004-04-28

    CPC classification number: H03L3/00

    Abstract: A crystal oscillator circuit which does not produce runt pulses when the oscillator is turned on or off. The circuit includes a crystal oscillator, an integrator which integrates the energy in a plurality of pulses, a threshold circuit which is active when the output of the integrator reaches a pre-specified threshold and gating circuits which gate the output of the crystal oscillator to the output terminal only when the threshold circuit has reached the specified threshold.

    Abstract translation: 振荡器开启或关闭时不产生欠压脉冲的晶振电路。 该电路包括晶体振荡器,积分器,其将多个脉冲中的能量进行积分;阈值电路,当积分器的输出达到预定阈值时有效;门控电路将晶体振荡器的输出选通到 输出端只有当阈值电路达到指定的阈值时。

    Fully integrated digital frequency synthesizer
    24.
    发明授权
    Fully integrated digital frequency synthesizer 有权
    全集成数字频率合成器

    公开(公告)号:US06188288B1

    公开(公告)日:2001-02-13

    申请号:US09229063

    申请日:1999-01-12

    CPC classification number: H03L7/1974 H03L7/085 H03L7/18 H03L2207/10

    Abstract: A frequency synthesizer apparatus is disclosed which combines a digital multiplier in the count down and phase comparison section with an oscillator entirely contained on an integrated circuit. Inclusion of the digital multiplier allows simultaneous realization of high loop bandwidth and fast tuning speed. The large loop bandwidth facilitates use of a totally integrated oscillator, which was heretofore not useable because of inferior phase noise characteristics. An integrated filter further enhances loop bandwidth while maintaining stability. Synchronizing the modulus switching of a multi-modulus prescaler with the multiplier coefficient minimizes spurious responses in the synthesized output.

    Abstract translation: 公开了一种频率合成器装置,其将倒数和相位比较部分中的数字乘法器与整体包含在集成电路上的振荡器组合。 数字乘法器的包含允许同时实现高环路带宽和快速调谐速度。 大环路带宽有利于使用完全集成的振荡器,这是迄今为止由于相位噪声特性较差而无法使用的。 集成滤波器进一步增强了环路带宽,同时保持了稳定性。 将多模预分频器的模数转换与乘法系数同步将合成输出中的杂散响应最小化。

    Digital receiver operating at sub-nyquist sampling rate
    25.
    发明授权
    Digital receiver operating at sub-nyquist sampling rate 失效
    数字接收机以亚妮基斯采样率运行

    公开(公告)号:US4893341A

    公开(公告)日:1990-01-09

    申请号:US388186

    申请日:1989-08-01

    Inventor: Mark R. Gehring

    CPC classification number: H03D1/2254 H04B1/1646

    Abstract: A digital receiver samples data from an amplitude modulated subcarrier at a rate less than twice the subcarrier's maximum frequency by sampling at known phase points. Sampling at known phase points is achieved by generating a sampling clock from a signal phase locked to and transmitted with the modulated data subcarrier.

Patent Agency Ranking