公开(公告)号：US11749353B2

公开(公告)日：2023-09-05

申请号：US17745852

申请日：2022-05-16

Applicant: Micron Technology, Inc.

Inventor： Kalyan Chakravarthy Kavalipurapu ,  Tomoko Ogura Iwasaki ,  Erwin E. Yu ,  Hong-Yan Chen ,  Yunfei Xu

IPC: G11C16/16 ,  G06F3/06 ,  G11C16/04 ,  G11C16/08

CPC classification number: G11C16/16 ,  G06F3/0604 ,  G06F3/064 ,  G06F3/0652 ,  G06F3/0679 ,  G11C16/0483 ,  G11C16/08

Abstract: A processing device in a memory system receives an erase request to erase data stored at a data block of a memory device, the erase request identifying a selected sub-block of a plurality of sub-blocks of the data block for erase, each of the plurality of sub-blocks comprising select gate devices (SGDs) and data storage devices. For each sub-block of the plurality of sub-blocks not selected for erase, the processing device applies an input voltage at a bitline of the respective sub-block and applies a plurality of gate voltages to a plurality of wordlines of the respective sub-block, the plurality of wordlines are coupled to the SGDs and to the data storage devices, each voltage of the plurality of voltages applied to a successive wordline of the plurality of wordlines is less than a previous voltage applied to a previous wordline.

公开(公告)号：US20230162796A1

公开(公告)日：2023-05-25

申请号：US17959171

申请日：2022-10-03

Applicant: Micron Technology, Inc.

Inventor： Hong-Yan Chen ,  Ching-Huang Lu

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/10 ,  G11C16/32

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/10 ,  G11C16/32

Abstract: Control logic in a memory device causes a program voltage to be applied to a selected data wordline of a plurality of wordlines of a block of a memory array for a pulse duration period during a programming operation. The control logic further causes a first pass voltage to be applied to one or more unselected data wordlines of the plurality of wordlines of the block for the pulse duration period and causes a second pass voltage to be applied to a last unselected data wordline of the plurality of wordlines of the block for at least a first portion of the pulse duration period, wherein the second pass voltage has a lower magnitude than the first pass voltage.

公开(公告)号：US20210391024A1

公开(公告)日：2021-12-16

申请号：US16946273

申请日：2020-06-12

Applicant: Micron Technology, Inc.

Inventor： Hong-Yan Chen ,  Yingda Dong

IPC: G11C16/34 ,  G11C16/10 ,  G11C16/26 ,  G11C16/08

Abstract: Control logic in a memory device initiates a program operation on the memory device, the program operation comprising a program phase, a program recovery phase, a program verify phase, and a program verify recovery phase. The control logic further causes a negative voltage signal to be applied to a first plurality of word lines of a data bock of the memory device during the program verify recovery phase of the program operation, wherein each of the first plurality of word lines is coupled to a corresponding memory cell of a first plurality of memory cells in a string of memory cells in the data block, the first plurality of word lines comprising a selected word line associated with the program operation and one or more data word lines adjacent to the selected word line.