公开(公告)号：US11289137B2

公开(公告)日：2022-03-29

申请号：US16171831

申请日：2018-10-26

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G11C7/10 ,  H04L47/10 ,  G06F13/18 ,  G06F13/16

Abstract: Methods, systems, and devices for a multi-port storage-class memory interface are described. A memory controller of the storage-class memory subsystem may receive, from a host device, a request associated with host addresses. The memory controller may generate interleaved addresses with a low latency based on the host addresses. The interleaved addresses parallelize processing of the request utilizing a set of memory media ports. Each memory media port of the set of memory media port may operate independent of each other to obtain a desired aggregated data transfer rate and a memory capacity. The interleaved address may leave no gaps in memory space. The memory controller may control a wear-leveling operation to distribute access operations across one or more zones of the memory media port.

公开(公告)号：US20220066949A1

公开(公告)日：2022-03-03

申请号：US17468160

申请日：2021-09-07

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G06F12/12 ,  G06F12/0804 ,  H03M13/27 ,  H03M13/00 ,  G06F12/0891

Abstract: Methods, systems, and devices for codeword rotation for zone grouping of media codewords are described. A value of a first pointer may be configured to correspond to a first memory address within a region of memory and a value of a second pointer may be configured to correspond to a second memory address within the region of memory. The method may include monitoring access commands for performing access operations within the region of memory, where the plurality of access command may be associated with requested addresses within the region of memory. The method may include updating the value of the second pointer bases on a quantity of the commands that are monitored satisfying a threshold and executing the plurality of commands on locations within the region of memory. The locations may be based on the requested address, the value of the first pointer, and the value of the second pointer.

公开(公告)号：US10831389B2

公开(公告)日：2020-11-10

申请号：US16551484

申请日：2019-08-26

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G06F11/00 ,  G11C29/00 ,  G06F3/06 ,  G06F11/10

Abstract: Methods, systems, and devices for code word formats and structures are described. A code word format and structure may include various fields that facilitate a reliable transaction of user data during an access operation associated with a memory medium. For example, the bit fields may include information directed to an error control operation for a port manager to perform on a code word configured in accordance with the code word format and structure. Additionally, the code word format and structure may be configured for low latency operation and reliable transaction of the user data during the access operation. For example, the port manager may receive a first portion of the code word and parse the first portion of the code word concurrently with receiving an additional portion of the code word.

公开(公告)号：US11853158B2

公开(公告)日：2023-12-26

申请号：US17690682

申请日：2022-03-09

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G06F11/00 ,  G06F11/10 ,  G11C11/409

CPC classification number: G06F11/102 ,  G06F11/1056 ,  G11C11/409

Abstract: Methods, systems, and devices for erroneous bit discovery in a memory system are described. A controller or memory controller, for example, may read a code word from a memory medium. The code word may include a set of bits that each correspond to a respective Minimum Substitution Region (MSR) of the memory medium. Each MSR may include a portion of memory cells of the memory medium and be associated with a counter to count a quantity of erroneous bits in each MSR. When the controller identifies a quantity of erroneous bits in the code word using an error control operation, the controller may update values of counters associated with respective MSRs that correspond to the quantity of erroneous bits to count erroneous bit counts for each MSR. In some cases, the controller may perform operations described herein as part of a background operation.

公开(公告)号：US11783876B2

公开(公告)日：2023-10-10

申请号：US17690907

申请日：2022-03-09

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G11C7/10 ,  H04L47/10 ,  G06F13/18 ,  G06F13/16

CPC classification number: G11C7/1075 ,  G06F13/16 ,  G06F13/18 ,  H04L47/10

Abstract: Methods, systems, and devices for a multi-port storage-class memory interface are described. A memory controller of the storage-class memory subsystem may receive, from a host device, a request associated with host addresses. The memory controller may generate interleaved addresses with a low latency based on the host addresses. The interleaved addresses parallelize processing of the request utilizing a set of memory media ports. Each memory media port of the set of memory media port may operate independent of each other to obtain a desired aggregated data transfer rate and a memory capacity. The interleaved address may leave no gaps in memory space. The memory controller may control a wear-leveling operation to distribute access operations across one or more zones of the memory media port.

公开(公告)号：US20220188250A1

公开(公告)日：2022-06-16

申请号：US17682908

申请日：2022-02-28

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Joseph Thomas Pawlowski ,  Elliott Cooper-Balis

IPC: G06F13/16 ,  G06F3/06 ,  G06F1/324 ,  G06F1/10

Abstract: Techniques for implementing and/or operating an apparatus, which includes a host system, a memory system, and a shared memory bus. The memory system includes a first memory type that is subject to a first memory type-specific timing constraint and a second memory type that is subject to a second memory type-specific timing constraint. Additionally, the shared memory bus is shared by the first memory type and the second memory type. Furthermore, the apparatus utilizes a first time period to communicate with the first memory type via the shared memory bus at least in part by enforcing the first memory type-specific timing constraint during the first time period and utilizes a second time period to communicate with the second memory type via the shared memory bus at least in part by enforcing the second memory type-specific timing constraint during the second time period.

公开(公告)号：US20220121515A1

公开(公告)日：2022-04-21

申请号：US17562244

申请日：2021-12-27

Applicant: Micron Technology, Inc.

Inventor： Joseph Thomas Pawlowski

IPC: G06F11/10 ,  G06F3/06

Abstract: Methods, systems, and devices for media scrubber operations in a memory system are described. A controller may, for example, count a quantity of forwarded code words in a memory medium during a scrubbing period. The controller may add the quantity to a total quantity of forwarded code words in the memory medium. The controller may refrain from forwarding additional code words based on the quantity. The controller may write a valid logic state to a spare bit when the spare bit is assigned to an erroneous bit in a code word. A separate memory cell may indicate a change in spare bit assignments and whether spare bits include valid logic states. The controller may retrieve a code word from a memory medium and invert one or more bits of the code word before writing the code word to the memory medium.

公开(公告)号：US11281604B2

公开(公告)日：2022-03-22

申请号：US16804895

申请日：2020-02-28

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Joseph Thomas Pawlowski ,  Elliott Cooper-Balis

IPC: G06F1/324 ,  G06F13/16 ,  G06F3/06 ,  G06F1/10

Abstract: Techniques for implementing and/or operating an apparatus, which includes a host system, a memory system, and a shared memory bus. The memory system includes a first memory type that is subject to a first memory type-specific timing constraint and a second memory type that is subject to a second memory type-specific timing constraint. Additionally, the shared memory bus is shared by the first memory type and the second memory type. Furthermore, the apparatus utilizes a first time period to communicate with the first memory type via the shared memory bus at least in part by enforcing the first memory type-specific timing constraint during the first time period and utilizes a second time period to communicate with the second memory type via the shared memory bus at least in part by enforcing the second memory type-specific timing constraint during the second time period.

公开(公告)号：US20220058132A1

公开(公告)日：2022-02-24

申请号：US16997811

申请日：2020-08-19

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Joseph Thomas Pawlowski

IPC: G06F12/0895 ,  G06F12/0862

Abstract: Described apparatuses and methods partition a cache memory based, at least in part, on a metric indicative of prefetch performance. The amount of cache memory allocated for metadata related to prefetch operations versus cache storage can be adjusted based on operating conditions. Thus, the cache memory can be partitioned into a first portion allocated for metadata pertaining to an address space (prefetch metadata) and a second portion allocated for data associated with the address space (cache data). The amount of cache memory allocated to the first portion can be increased under workloads that are suitable for prefetching and decreased otherwise. The first portion may include one or more cache units, cache lines, cache ways, cache sets, or other resources of the cache memory.

公开(公告)号：US20210365376A1

公开(公告)日：2021-11-25

申请号：US16880248

申请日：2020-05-21

Applicant: Micron Technology, Inc.

Inventor： David Andrew Roberts ,  Joseph Thomas Pawlowski

IPC: G06F12/0815 ,  G06F12/0804

Abstract: Described apparatuses and methods form adaptive cache lines having a configurable capacity from hardware cache lines having a fixed capacity. The adaptive cache lines can be formed in accordance with a programmable cache-line parameter. The programmable cache-line parameter can specify a capacity for the adaptive cache lines. The adaptive cache lines may be formed by combining respective groups of fixed-capacity hardware cache lines. The quantity of fixed-capacity hardware cache lines included in respective adaptive cache lines may be based on the programmable cache-line parameter. The programmable cache-line parameter can be selected in accordance with characteristics of the cache workload.