公开(公告)号：US10162406B1

公开(公告)日：2018-12-25

申请号：US15692852

申请日：2017-08-31

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Kallol Mazumder ,  Parthasarathy Gajapathy

IPC: G11C11/4076 ,  G06F3/00 ,  G11C7/10 ,  G06F13/16 ,  G11C11/4063

Abstract: The systems and methods provided herein identify a command acquisition mode from a plurality of command acquisition modes of a command interface of a memory device. A state of a chip select signal (CS) is identified. When the CS transitions to low from high, a first portion of a command address is captured in a first clock cycle after the CS transitions. When the command acquisition mode is in a first mode, a second portion of the command address is captured in a second clock cycle immediately after the first clock cycle. Otherwise, when the command acquisition mode is in a second mode, the second portion of the command address is captured in a third clock cycle immediately following the second clock signal. An internal command is fired, using the first portion of the command address and the second portion of the command address.

公开(公告)号：US20180247682A1

公开(公告)日：2018-08-30

申请号：US15965263

申请日：2018-04-27

Applicant: MICRON TECHNOLOGY, INC.

Inventor： Parthasarathy Gajapathy

IPC: G11C7/12 ,  G11C7/10 ,  G11C11/4076 ,  G11C8/18

CPC classification number: G11C7/12 ,  G11C7/1018 ,  G11C8/18 ,  G11C11/4076

Abstract: Disclosed are methods for reading data from a storage buffer. One such method may include retrieving a first set of data during a first period of time. The method may also include delaying data retrieval during a second period of time after the first period of time. The method may include outputting at least a portion of the first set of data during the first period of time and the second period of time. The first period of time is substantially similar to the second period of time.

公开(公告)号：US09570125B1

公开(公告)日：2017-02-14

申请号：US15070670

申请日：2016-03-15

Applicant: Micron Technology, Inc.

Inventor： Parthasarathy Gajapathy

IPC: G11C7/10

CPC classification number: G11C7/1078 ,  G11C7/1009 ,  G11C7/1012 ,  G11C7/1084 ,  G11C7/1087

Abstract: Apparatuses and methods are provided that include a multiplexer configured to generate a plurality of sums of a plurality of data words, wherein the plurality of data words is received by the multiplexer and identified as unmasked based on a data mask. The multiplexer is also configured to determine whether each sum of the plurality of sums indicates that a corresponding data word of the plurality of data words is masked. The multiplexer is further configured to shift the plurality of data words to remove the corresponding masked data word from the plurality of data words. The multiplexer is also configured to output only the data words identified as unmasked based on the data mask.

Abstract translation: 提供了包括多路复用器的设备和方法，所述多路复用器被配置为生成多个数据字的多个和，其中所述多个数据字被所述多路复用器接收并且基于数据掩码被识别为未屏蔽。 多路复用器还被配置为确定多个和的每个和是否表示多个数据字中的相应数据字被掩蔽。 复用器还被配置为移位多个数据字以从多个数据字中移除相应的屏蔽数据字。 复用器还被配置为仅输出基于数据掩码识别为未屏蔽的数据字。

公开(公告)号：US20150170731A1

公开(公告)日：2015-06-18

申请号：US14133272

申请日：2013-12-18

Applicant: Micron Technology, Inc.

Inventor： Parthasarathy Gajapathy ,  David R. Brown

IPC: G11C11/4093

CPC classification number: G11C11/4093 ,  G11C7/1009

Abstract: Disclosed are apparatuses and methods for writing data to a memory array of a buffer. One such apparatus may include a multiplexer that receives data words and a data mask. The multiplexer may change the order of the data words to group masked data words together and to group unmasked data words together. The multiplexer may also change the order of the data mask to group masking bits together and to group unmasking bits together. The apparatus may use the data words with the changed order and the data mask with the changed order to write data to the memory array.

Abstract translation: 公开了将数据写入缓冲器的存储器阵列的装置和方法。 一种这样的装置可以包括接收数据字和数据掩码的多路复用器。 复用器可以将数据字的顺序改变为将屏蔽的数据字组合在一起，并将未屏蔽的数据字组合在一起。 多路复用器还可以将数据掩码的顺序改变为组屏蔽位在一起，并且将未屏蔽位组合在一起。 设备可以使用具有改变顺序的数据字和具有改变顺序的数据掩码将数据写入存储器阵列。

公开(公告)号：US08570826B2

公开(公告)日：2013-10-29

申请号：US13672018

申请日：2012-11-08

Applicant: Micron Technology, Inc.

Inventor： Parthasarathy Gajapathy

IPC: G11C8/00

CPC classification number: G11C7/1075 ,  G11C11/4096 ,  G11C11/4097

Abstract: Apparatus and methods are disclosed, such as those involving array/port consolidation and/or swapping. One such apparatus includes a plurality of port pads including a plurality of contacts; a plurality of memory arrays; and a plurality of master data lines. Each of the master data lines extends in a space between one of the port pads and a respective one of the memory arrays. Each of the master data lines is electrically connectable to the contacts of a respective one of the port pads. The apparatus further includes a plurality of local data lines, each of which extends over a respective one of the memory arrays. Each of the local data lines is electrically connectable to a respective one of the master data lines. At least one of the local data lines extends over at least two of the memory arrays. This configuration allows memory array consolidation and/or swapping without increasing die space for additional routing and adversely affecting performance of the apparatus.

Abstract translation: 公开了装置和方法，例如涉及阵列/端口整合和/或交换的装置和方法。 一种这样的设备包括多个端口焊盘，其包括多个触点; 多个存储器阵列; 和多条主数据线。 每个主数据线在一个端口焊盘和相应的一个存储器阵列之间的空间中延伸。 每个主数据线可电连接到相应一个端口焊盘的触头。 该装置还包括多个本地数据线，每个本地数据线在相应的一个存储器阵列上延伸。 每个本地数据线可电连接到相应的主数据线之一。 至少一个本地数据线延伸至少两个存储器阵列。 该配置允许存储器阵列整合和/或交换，而不增加管芯空间用于额外的路由并且不利地影响设备的性能。