公开(公告)号：US20130154029A1

公开(公告)日：2013-06-20

申请号：US13611068

申请日：2012-09-12

申请人： Ming Cai ,  Dechao Guo ,  Pranita Kulkarni ,  Chun-Chen Yeh

发明人： Ming Cai ,  Dechao Guo ,  Pranita Kulkarni ,  Chun-Chen Yeh

IPC分类号： H01L29/78

CPC分类号： H01L29/66795 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/785

摘要： Multigate transistor devices and methods of their fabrication are disclosed. In accordance with one method, a fin and a gate structure that is disposed on a plurality of surfaces of the fin are formed. In addition, at least a portion of an extension of the fin is removed to form a recessed portion that is below the gate structure, is below a channel region of the fin, and includes at least one angled indentation. Further, a terminal extension is grown in the at least one angled indentation below the channel region and along a surface of the channel region such that the terminal extension provides a stress on the channel region to enhance charge carrier mobility in the channel region.

公开(公告)号：US20120286375A1

公开(公告)日：2012-11-15

申请号：US13103149

申请日：2011-05-09

申请人： Ming Cai ,  Dechao Guo ,  Pranita Kulkarni ,  Chun-Chen Yeh

发明人： Ming Cai ,  Dechao Guo ,  Pranita Kulkarni ,  Chun-Chen Yeh

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L21/823412 ,  H01L21/0217 ,  H01L21/02345 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/3105 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A method of forming a semiconductor structure includes forming a stress inducing layer over one or more partially completed field effect transistor (FET) devices disposed over a substrate, the one or more partially completed FET devices including sacrificial dummy gate structures; planarizing the stress inducing layer and removing the sacrificial dummy gate structures; and following the planarizing the stress inducing layer and removing the sacrificial dummy gate structures, performing an ultraviolet (UV) cure of the stress inducing layer so as to enhance a value of an initial applied stress by the stress inducing layer on channel regions of the one or more partially completed FET devices.

摘要翻译： 形成半导体结构的方法包括在设置在衬底上的一个或多个部分完成的场效应晶体管（FET）器件上形成应力感应层，所述一个或多个部分完成的FET器件包括牺牲虚拟栅极结构; 平面化应力诱导层并去除牺牲虚拟栅极结构; 并且在平坦化应力诱导层并去除牺牲性虚拟栅极结构之后，执行应力诱导层的紫外（UV）固化，以便增强应力诱导层在一个沟道区上的初始施加应力的值 或更多部分完成的FET器件。

公开(公告)号：US08658505B2

公开(公告)日：2014-02-25

申请号：US13325506

申请日：2011-12-14

申请人： Ming Cai ,  Dechao Guo ,  Pranita Kulkarni ,  Chun-Chen Yeh

发明人： Ming Cai ,  Dechao Guo ,  Pranita Kulkarni ,  Chun-Chen Yeh

IPC分类号： H01L21/336

CPC分类号： H01L29/66795 ,  H01L29/165 ,  H01L29/7848 ,  H01L29/785

摘要： Multigate transistor devices and methods of their fabrication are disclosed. In accordance with one method, a fin and a gate structure that is disposed on a plurality of surfaces of the fin are formed. In addition, at least a portion of an extension of the fin is removed to form a recessed portion that is below the gate structure, is below a channel region of the fin, and includes at least one angled indentation. Further, a terminal extension is grown in the at least one angled indentation below the channel region and along a surface of the channel region such that the terminal extension provides a stress on the channel region to enhance charge carrier mobility in the channel region.

公开(公告)号：US08648438B2

公开(公告)日：2014-02-11

申请号：US13251660

申请日：2011-10-03

申请人： Ming Cai ,  Dechao Guo ,  Chun-Chen Yeh

发明人： Ming Cai ,  Dechao Guo ,  Chun-Chen Yeh

IPC分类号： H01L23/525

CPC分类号： H01L27/1203 ,  H01L21/84 ,  H01L27/13

摘要： Techniques for fabricating passive devices in an extremely-thin silicon-on-insulator (ETSOI) wafer are provided. In one aspect, a method for fabricating one or more passive devices in an ETSOI wafer is provided. The method includes the following steps. The ETSOI wafer having a substrate and an ETSOI layer separated from the substrate by a buried oxide (BOX) is provided. The ETSOI layer is coated with a protective layer. At least one trench is formed that extends through the protective layer, the ETSOI layer and the BOX, and wherein a portion of the substrate is exposed within the trench. Spacers are formed lining sidewalls of the trench. Epitaxial silicon templated from the substrate is grown in the trench. The protective layer is removed from the ETSOI layer. The passive devices are formed in the epitaxial silicon.

摘要翻译： 提供了在极薄的绝缘体上硅（ETSOI）晶圆上制造无源器件的技术。 在一方面，提供了一种用于在ETSOI晶片中制造一个或多个无源器件的方法。 该方法包括以下步骤。 提供具有衬底的ETSOI晶片和通过掩埋氧化物（BOX）与衬底分离的ETSOI层。 ETSOI层涂有保护层。 形成延伸穿过保护层，ETSOI层和BOX的至少一个沟槽，并且其中衬底的一部分暴露在沟槽内。 在沟槽的侧壁上形成间隔物。 从衬底模板化的外延硅在沟槽中生长。 保护层从ETSOI层去除。 无源器件形成在外延硅中。

公开(公告)号：US08421132B2

公开(公告)日：2013-04-16

申请号：US13103149

申请日：2011-05-09

申请人： Ming Cai ,  Dechao Guo ,  Pranita Kulkarni ,  Chun-Chen Yeh

发明人： Ming Cai ,  Dechao Guo ,  Pranita Kulkarni ,  Chun-Chen Yeh

IPC分类号： H01L29/76 ,  H01L21/336

CPC分类号： H01L21/823412 ,  H01L21/0217 ,  H01L21/02345 ,  H01L21/28088 ,  H01L21/28114 ,  H01L21/3105 ,  H01L21/823425 ,  H01L21/823437 ,  H01L21/823807 ,  H01L21/823828 ,  H01L29/42376 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/6659 ,  H01L29/7833 ,  H01L29/7843

摘要： A method of forming a semiconductor structure includes forming a stress inducing layer over one or more partially completed field effect transistor (FET) devices disposed over a substrate, the one or more partially completed FET devices including sacrificial dummy gate structures; planarizing the stress inducing layer and removing the sacrificial dummy gate structures; and following the planarizing the stress inducing layer and removing the sacrificial dummy gate structures, performing an ultraviolet (UV) cure of the stress inducing layer so as to enhance a value of an initial applied stress by the stress inducing layer on channel regions of the one or more partially completed FET devices. A semiconductor structure includes a UV cured tensile nitride layer formed over the substrate and between gate structures of the NFET devices, with portions of the UV cured tensile nitride layer having a trapezoidal profile with a bottom end wider than a top end.

摘要翻译： 形成半导体结构的方法包括在设置在衬底上的一个或多个部分完成的场效应晶体管（FET）器件上形成应力感应层，所述一个或多个部分完成的FET器件包括牺牲虚拟栅极结构; 平面化应力诱导层并去除牺牲虚拟栅极结构; 并且在平坦化应力诱导层并去除牺牲性虚拟栅极结构之后，执行应力诱导层的紫外（UV）固化，以便增强应力诱导层在一个沟道区上的初始施加应力的值 或更多部分完成的FET器件。 半导体结构包括形成在衬底上和NFET器件的栅极结构之间的UV固化的拉伸氮化物层，其中UV固化的拉伸氮化物层的一部分具有比顶端更宽的底端的梯形轮廓。

公开(公告)号：US09158409B2

公开(公告)日：2015-10-13

申请号：US13142374

申请日：2010-09-27

申请人： Lei Lv ,  Ming Cai ,  Yuan Yao

发明人： Lei Lv ,  Ming Cai ,  Yuan Yao

IPC分类号： G06F3/041 ,  G06F3/0488 ,  H04M1/725 ,  G06F3/0481 ,  G06F3/0486 ,  G06F3/0484

CPC分类号： G06F3/0416 ,  G06F3/04817 ,  G06F3/04842 ,  G06F3/0486 ,  G06F3/0488 ,  H04M1/72583 ,  H04M2250/22

摘要： The embodiments of the invention disclose an object determining method, a portable device, an object displaying method, an object switching method and an electronic device. Said method is applied to a touch sensitive portable device. Identifications of multiple objects are displayed within a display area of said portable device. Each of the identifications of said multiple objects has a first status of being selected and a second status of being unselected. Said display area has a first area, the identification of a first object is displayed in the first area, and the first object is in the first status. Said method comprises: obtaining a switch instruction; moving the identification of the first object of the first area, switching the identification of the first object from the first status to the second status, moving the identification of the second object into the first area, and switching the identification of the second object from the second status to the first status according to the switch instruction. The embodiments of the invention can simplify the steps of the user's operation.

摘要翻译： 本发明的实施例公开了一种对象确定方法，便携式设备，对象显示方法，对象切换方法和电子设备。 所述方法应用于触敏便携式设备。 多个对象的识别显示在所述便携式设备的显示区域内。 所述多个对象的每个标识具有被选择的第一状态和未被选择的第二状态。 所述显示区域具有第一区域，第一对象的识别显示在第一区域中，并且第一对象处于第一状态。 所述方法包括：获取开关指令; 移动第一区域的第一对象的识别，将第一对象的识别从第一状态切换到第二状态，将第二对象的标识移动到第一区域，并且将第二对象的标识从 根据切换指令将第二状态转为第一状态。 本发明的实施例可以简化用户操作的步骤。

公开(公告)号：US20120306793A1

公开(公告)日：2012-12-06

申请号：US13497307

申请日：2010-09-21

申请人： Xiangtao Liu ,  Dayong Gan ,  Lei Lv ,  Rong Zhang ,  Ming Cai ,  Nan Wang

发明人： Xiangtao Liu ,  Dayong Gan ,  Lei Lv ,  Rong Zhang ,  Ming Cai ,  Nan Wang

IPC分类号： G06F3/041

CPC分类号： G06F3/04886 ,  G06F3/04883 ,  H04M2250/22

摘要： A touch-input device and an electronic device and a cell phone are described and include a touch acquisition module with an input area to execute touch acquisition operations. The input area includes a first area and a second area. A pointing object location module is used to determine the start location of the touch operation according to the data acquired by the touch acquisition module. A process module is used to calculate a first result indicating the coordinate of the pointing object according to the data acquired by the touch acquisition module when the start location of the touch operation is in the first area, and to calculate a second result indicating the movement of the pointing object according to the data acquired by the touch acquisition module when the start location of the touch operation is in the second area.

摘要翻译： 描述了触摸输入设备和电子设备以及手机，并且包括具有用于执行触摸获取操作的输入区域的触摸获取模块。 输入区域包括第一区域和第二区域。 指示对象定位模块用于根据由触摸获取模块获取的数据确定触摸操作的开始位置。 当触摸操作的开始位置处于第一区域时，处理模块用于根据由触摸获取模块获取的数据计算指示对象的坐标的第一结果，并计算指示移动的第二结果 根据在触摸操作的开始位置处于第二区域时由触摸获取模块获取的数据的指示对象。

公开(公告)号：US20120292670A1

公开(公告)日：2012-11-22

申请号：US13108240

申请日：2011-05-16

申请人： Ming Cai ,  Ahmet S. Ozcan

发明人： Ming Cai ,  Ahmet S. Ozcan

IPC分类号： H01L21/28 ,  H01L29/78

CPC分类号： H01L21/265 ,  H01L21/268 ,  H01L29/665 ,  H01L29/78 ,  H01L29/7843

摘要： A method of fabricating a semiconductor device and a corresponding semiconductor device are provided. The method can include implanting a species into a silicide region, the silicide region contacting a semiconductor region of a substrate. A stressed liner may then be formed overlying the silicide region having the implanted species therein. In a particular example, prior to forming the stressed liner, a step of annealing can be performed within an interval less than one second to elevate at least a portion of the silicide region to a peak temperature ranging from 800 to 950° C. The method may reduce the chance of deterioration in the silicide region, e.g., the risk of void formation, due to processing used to form the stressed liner.

摘要翻译： 提供了制造半导体器件和相应的半导体器件的方法。 该方法可以包括将物质植入到硅化物区域中，硅化物区域接触衬底的半导体区域。 然后可以在其中具有植入物质的硅化物区域上形成应力衬垫。 在特定实例中，在形成应力衬垫之前，可以在小于1秒的间隔内进行退火步骤，以将至少一部分硅化物区域提升到800-950℃的峰值温度。方法 可能减少由于用于形成应力衬里的加工而导致硅化物区域劣化的机会，例如形成空隙的风险。

公开(公告)号：US20120218196A1

公开(公告)日：2012-08-30

申请号：US13142374

申请日：2010-09-27

申请人： Lei Lv ,  Ming Cai ,  Yuan Yao

发明人： Lei Lv ,  Ming Cai ,  Yuan Yao

IPC分类号： G06F3/041

CPC分类号： G06F3/0416 ,  G06F3/04817 ,  G06F3/04842 ,  G06F3/0486 ,  G06F3/0488 ,  H04M1/72583 ,  H04M2250/22

摘要： The embodiments of the invention disclose an object determining method, a portable device, an object displaying method, an object switching method and an electronic device. Said method is applied to a touch sensitive portable device. Identifications of multiple objects are displayed within a display area of said portable device. Each of the identifications of said multiple objects has a first status of being selected and a second status of being unselected. Said display area has a first area, the identification of a first object is displayed in the first area, and the first object is in the first status. Said method comprises: obtaining a switch instruction; moving the identification of the first object of the first area, switching the identification of the first object from the first status to the second status, moving the identification of the second object into the first area, and switching the identification of the second object from the second status to the first status according to the switch instruction. The embodiments of the invention can simplify the steps of the user's operation.

摘要翻译： 本发明的实施例公开了一种对象确定方法，便携式设备，对象显示方法，对象切换方法和电子设备。 所述方法应用于触敏便携式设备。 多个对象的识别显示在所述便携式设备的显示区域内。 所述多个对象的每个标识具有被选择的第一状态和未被选择的第二状态。 所述显示区域具有第一区域，第一对象的识别显示在第一区域中，并且第一对象处于第一状态。 所述方法包括：获取开关指令; 移动第一区域的第一对象的识别，将第一对象的识别从第一状态切换到第二状态，将第二对象的标识移动到第一区域，并且将第二对象的标识从 根据切换指令将第二状态转为第一状态。 本发明的实施例可以简化用户操作的步骤。

公开(公告)号：US20120104500A1

公开(公告)日：2012-05-03

申请号：US12914095

申请日：2010-10-28

申请人： Ming Cai ,  Xi Li ,  Frank D. Tamweber, JR.

发明人： Ming Cai ,  Xi Li ,  Frank D. Tamweber, JR.

IPC分类号： H01L27/088 ,  H01L21/762

CPC分类号： H01L21/823481 ,  H01L21/76224 ,  H01L21/823468

摘要： A method of forming a semiconductor device includes forming a spacer layer over a plurality of transistor gate structures, the transistor gate structures being formed over both active and shallow trench isolation (STI) regions of a substrate. The spacer layer is subjected to a directional etch so as to form sidewall spacers adjacent the plurality of transistor gate structures, and a horizontal fill portion of the spacer layer remains in one more recesses present in the STI regions so as to substantially planarize the STI region prior to subsequent material deposition thereon.

摘要翻译： 形成半导体器件的方法包括在多个晶体管栅极结构上形成间隔层，晶体管栅极结构形成在衬底的有源和浅沟槽隔离（STI）区域上。 对间隔层进行定向蚀刻以形成与多个晶体管栅极结构相邻的侧壁间隔物，并且间隔层的水平填充部分保留在STI区域中存在的多个凹部中，以使STI区域基本平坦化 在其之后的材料沉积之前。