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公开(公告)号：US20100142107A1
公开(公告)日：2010-06-10
申请号：US12656495
申请日：2010-02-01
IPC分类号： H02H9/04
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor.
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公开(公告)号：US07656627B2
公开(公告)日：2010-02-02
申请号：US11826634
申请日：2007-07-17
IPC分类号： H02H9/00
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection circuit is provided. The circuit includes a discharging component, a diode, and an ESD detection circuit. The discharging component is coupled between an input/output pad and a first power line of an IC. The diode is coupled between the input/output pad and a second power line of the IC in a forward direction toward the second power line. The ESD detection circuit includes a capacitor, a resistor, and a triggering component. The capacitor and the resistor are formed in series and coupled between the first power line and the second power line. The triggering component has a positive power end coupled to the input/output pad and a negative power end coupled to the first power line. An input of the triggering component is coupled to a node between the capacitor and the resistor.
摘要翻译： 提供ESD保护电路。 电路包括放电元件，二极管和ESD检测电路。 放电元件耦合在IC的输入/输出焊盘和第一电源线之间。 所述二极管在所述输入/输出焊盘和所述IC的第二电源线之间朝向所述第二电力线向前方连接。 ESD检测电路包括电容器，电阻器和触发部件。 电容器和电阻器串联形成并耦合在第一电源线和第二电源线之间。 触发组件具有耦合到输入/输出焊盘的正功率端和耦合到第一电源线的负功率端。 触发元件的输入耦合到电容器和电阻器之间的节点。
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公开(公告)号：US20090273006A1
公开(公告)日：2009-11-05
申请号：US12149287
申请日：2008-04-30
申请人： Wen-Yi Chen , Ryan Hsin-Chin Jiang , Ming-Dou Ker
发明人： Wen-Yi Chen , Ryan Hsin-Chin Jiang , Ming-Dou Ker
IPC分类号： H01L29/72
CPC分类号： H01L29/747 , H01L27/0262 , H01L29/87
摘要： The present invention discloses a bidirectional silicon-controlled rectifier, wherein the conventional field oxide layer, which separates an anode structure from a cathode structure, is replaced by a field oxide layer having floating gates, a virtual gate or a virtual active region. Thus, the present invention can reduce or escape from the bird's beak effect of a field oxide layer, which results in crystalline defects, a concentrated current and a higher magnetic field and then causes abnormal operation of a rectifier. Thereby, the present invention can also reduce signal loss.
摘要翻译： 本发明公开了一种双向硅控整流器，其中将阳极结构与阴极结构分开的常规场氧化物层由具有浮动栅极，虚拟栅极或虚拟有源区域的场氧化物层代替。 因此，本发明可以减少或逃避场氧化物层的鸟喙作用，这导致晶体缺陷，集中电流和较高的磁场，然后导致整流器的异常操作。 由此，本发明也可以减少信号损失。
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公开(公告)号：US20090236631A1
公开(公告)日：2009-09-24
申请号：US12076556
申请日：2008-03-20
申请人： Wen-Yi Chen , Ryan Hsin-Chin Jiang , Ming-Dou Ker
发明人： Wen-Yi Chen , Ryan Hsin-Chin Jiang , Ming-Dou Ker
IPC分类号： H01L29/747
CPC分类号： H01L27/0262 , H01L29/747 , H01L29/87
摘要： The present invention discloses a bidirectional PNPN silicon-controlled rectifier comprising: a p-type substrate; a N-type epitaxial layer; a P-type well and two N-type wells all formed inside the N-type epitaxial layer with the two N-type wells respectively arranged at two sides of the P-type well; a first semiconductor area, a second semiconductor area and a third semiconductor area all formed inside the P-type well and all coupled to an anode, wherein the second semiconductor area and the third semiconductor area are respectively arranged at two sides of the first semiconductor area, and wherein the first semiconductor area is of first conduction type, and the second semiconductor area and the third semiconductor area are of second conduction type; and two P-type doped areas respectively formed inside the N-type wells, wherein each P-type doped area has a fourth semiconductor area neighboring the P-type well and a fifth semiconductor area, and wherein both the fourth semiconductor area and the fifth semiconductor area are coupled to a cathode, and wherein the fourth semiconductor area is of second conduction type, and the fifth semiconductor area is of first conduction type.
摘要翻译： 本发明公开了一种双向PNPN可控硅整流器，包括：p型衬底; N型外延层; 所有形成在N型外延层内的P型阱和两个N型阱，两个N型阱分别布置在P型阱的两侧; 所述第一半导体区域，第二半导体区域和第三半导体区域全部形成在所述P型阱内并全部耦合到阳极，其中所述第二半导体区域和所述第三半导体区域分别布置在所述第一半导体区域的第二半导体区域 并且其中所述第一半导体区域是第一导电类型，并且所述第二半导体区域和所述第三半导体区域是第二导电类型; 分别形成在N型阱内部的两个P型掺杂区域，其中每个P型掺杂区域具有与P型阱相邻的第四半导体区域和第五半导体区域，并且其中第四半导体区域和第五半导体区域 半导体区域耦合到阴极，并且其中第四半导体区域是第二导电类型，并且第五半导体区域是第一导电类型。
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公开(公告)号：US20090002028A1
公开(公告)日：2009-01-01
申请号：US11769716
申请日：2007-06-28
申请人： Ming-Dou Ker , Hui-Wen Tsai , Ryan Hsin-Chin Jiang
发明人： Ming-Dou Ker , Hui-Wen Tsai , Ryan Hsin-Chin Jiang
IPC分类号： H03K19/0175
CPC分类号： H03K19/00315
摘要： A Mixed-voltage input and output (I/O) buffer including a pre-driver unit, a bulk-voltage generating unit, a first to a third transistors and an input stage unit is provided. The pre-driver unit outputs a first source/drain and a second signal. The bulk-voltage generating unit determines whether a first voltage or a pad voltage is used as a bulk voltage according to the pad voltage level. A gate of the first transistor receives the first signal, and a bulk, a first source/drain and a second source/drain of the first transistor are respectively coupled to the bulk voltage, the first voltage and the pad. A gate of the third transistor receives the second signal, and a first source/drain and a second source/drain of the third transistor are respectively coupled to the input stage unit for receiving an input signal from the pad and a second voltage.
摘要翻译： 提供了包括预驱动器单元，体电压产生单元，第一至第三晶体管和输入级单元的混合电压输入和输出（I / O）缓冲器。 预驱动器单元输出第一源极/漏极和第二信号。 体积电压产生单元根据焊盘电压电平来确定是否使用第一电压或焊盘电压作为体电压。 第一晶体管的栅极接收第一信号，并且第一晶体管的体，第一源极/漏极和第二源极/漏极分别耦合到体电压，第一电压和焊盘。 第三晶体管的栅极接收第二信号，第三晶体管的第一源极/漏极和第二源极/漏极分别耦合到输入级单元，用于从焊盘接收输入信号和第二电压。
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公开(公告)号：US20130153957A1
公开(公告)日：2013-06-20
申请号：US13331241
申请日：2011-12-20
IPC分类号： H01L29/73
CPC分类号： H01L27/0262 , H01L29/861
摘要： A silicon-controlled-rectifier (SCR) with adjustable holding voltage is disclosed, which comprises a heavily doped semiconductor layer and an epitaxial layer formed on the heavily doped semiconductor layer. A first N-well having a first P-heavily doped area is formed in the epitaxial layer. A second N-well or a first P-well is formed in the epitaxial layer. When the second N-well is formed in the epitaxial layer, a P-doped area is located between the first N-well and the second N-well. Besides, a first N-heavily doped area is formed in the second N-well or the first P-well. At least one deep isolation trench is formed in the epitaxial layer and located between the first P-heavily doped area and the first N-heavily doped area. A distance between the deep isolation trench and the heavily doped semiconductor layer is larger than zero.
摘要翻译： 公开了具有可调保持电压的硅控整流器（SCR），其包括在重掺杂半导体层上形成的重掺杂半导体层和外延层。 在外延层中形成具有第一P重掺杂区的第一N阱。 在外延层中形成第二N阱或第一P阱。 当第二N阱形成在外延层中时，P掺杂区域位于第一N阱和第二N阱之间。 此外，在第二N阱或第一P阱中形成第一N重掺杂区。 在外延层中形成至少一个深的隔离沟槽，并且位于第一P重掺杂区域和第一N重掺杂区域之间。 深隔离沟槽和重掺杂半导体层之间的距离大于零。
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公开(公告)号：US20130127007A1
公开(公告)日：2013-05-23
申请号：US13303946
申请日：2011-11-23
IPC分类号： H01L29/06
CPC分类号： H01L27/0296 , H01L29/8613 , H01L29/866
摘要： A transient voltage suppressor without leakage current is disclosed, which comprises a P-substrate. There is an N-type epitaxial layer formed on the P-substrate, and a first N-heavily doped area, a first P-heavily doped area, an electrostatic discharge (ESD) device and at least one deep isolation trench are formed in the N-epitaxial layer. A first N-buried area is formed in the bottom of the N-epitaxial layer to neighbor the P-substrate and located below the first N-heavily doped area and the first P-heavily doped area. The ESD device is coupled to the first N-heavily doped area. The deep isolation trench is not only adjacent to the first N-heavily doped area, but has a depth greater than a depth of the first N-buried area, thereby separating the first N-buried area and the ESD device.
摘要翻译： 公开了一种无泄漏电流的瞬态电压抑制器，其包括P型衬底。 在P基板上形成有N型外延层，在第一N重掺杂区，第一P重掺杂区，静电放电（ESD）器件和至少一个深隔离沟槽中形成第一N重掺杂区， N外延层。 在N外延层的底部形成第一N区，以邻近P衬底并且位于第一N重掺杂区和第一P重掺杂区的下方。 ESD器件耦合到第一N重掺杂区域。 深隔离沟槽不仅与第一N重掺杂区相邻，而且具有大于第一N埋入区深度的深度，从而分离第一N埋区和ESD器。
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公开(公告)号：US20120241903A1
公开(公告)日：2012-09-27
申请号：US13072138
申请日：2011-03-25
IPC分类号： H01L29/66
CPC分类号： H01L27/0255 , H01L29/861
摘要： A low capacitance transient voltage suppressor is disclosed. The suppressor comprises an N-type heavily doped substrate and an epitaxial layer formed on the substrate. At least one steering diode structure formed in the epitaxial layer comprises a diode lightly doped well and a first P-type lightly doped well, wherein a P-type heavily doped area is formed in the diode lightly doped well and a first N-type heavily doped area and a second P-type heavily doped area are formed in the first P-type lightly doped well. A second P-type lightly doped well having two N-type heavily doped areas is formed in the epitaxial layer. In addition, an N-type heavily doped well and at least one deep isolation trench are formed in the epitaxial layer, wherein the trench has a depth greater than or equal to depths of all the doped wells, so as to separate at least one doped well.
摘要翻译： 公开了一种低电容瞬态电压抑制器。 抑制器包括N型重掺杂衬底和形成在衬底上的外延层。 形成在外延层中的至少一个转向二极管结构包括二极管轻掺杂阱和第一P型轻掺杂阱，其中在二极管轻掺杂阱中形成P型重掺杂区，并且第一N型重掺杂阱 在第一P型轻掺杂阱中形成掺杂区域和第二P型重掺杂区域。 在外延层中形成具有两个N型重掺杂区的第二P型轻掺杂阱。 此外，在外延层中形成N型重掺杂阱和至少一个深隔离沟槽，其中沟槽的深度大于或等于所有掺杂阱的深度，以便分离至少一个掺杂的 好。
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公开(公告)号：US20120018778A1
公开(公告)日：2012-01-26
申请号：US12840749
申请日：2010-07-21
IPC分类号： H01L27/06
CPC分类号： H01L27/0259
摘要： A new ESD protection device with an integrated-circuit vertical transistor structure is disclosed, which includes a heavily doped p-type substrate (P+ substrate), a n-type well (N well) in the P+ substrate, a heavily doped p-type diffusion (P+ diffusion) in the N well, a heavily doped n-type diffusion (N+ diffusion) in the N well, and a p-type well (P well) surrounding the N well in the P+ substrate. A bond pad is connected to both the P+ and N+ diffusions, and a ground is coupled to the P+ substrate. Another P+ diffusion is implanted in the N well or another N+ diffusion is implanted in the P well to form a Zener diode, which behaves as a trigger for the PNP transistor when a positive ESD zaps. A parasitic diode is formed at the junction between the P+ substrate and the N well, to bypass a negative ESD stress on the bond pad.
摘要翻译： 公开了一种具有集成电路垂直晶体管结构的新型ESD保护器件，其包括重掺杂p型衬底（P +衬底），P +衬底中的n型阱（N阱），重掺杂p型衬底 N阱中的扩散（P +扩散），N阱中的重掺杂n型扩散（N +扩散）以及P +衬底中N阱周围的p型阱（P阱）。 接合焊盘连接到P +和N +扩散两者，并且接地耦合到P +衬底。 将另一个P +扩散注入到N阱中，或者将另一个N +扩散注入到P阱中以形成齐纳二极管，当正ESD成像时，其作为PNP晶体管的触发器。 在P +衬底和N阱之间的接合处形成寄生二极管，以绕过接合焊盘上的负ESD应力。
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公开(公告)号：US20120014027A1
公开(公告)日：2012-01-19
申请号：US12836745
申请日：2010-07-15
IPC分类号： H02H3/22
CPC分类号： H02H9/046 , H05K1/0259
摘要： A transient voltage suppressor (TVS) for multiple pin assignments is disclosed. The suppressor comprises at least two cascade-diode circuits in parallel to each other and an electrostatic-discharge clamp element in parallel to each cascade-diode circuit and connected with a low voltage. One cascade-diode circuit is connected with a high voltage, and the other cascade-diode circuits are respectively connected with I/O pins. Each cascade-diode circuit further comprises a first diode and a second diode cascaded to the first diode, wherein a node between the first diode and the second diode is connected with the high voltage or the one I/O pin. The design of the present invention can meet several bounding requirements. It is flexible different pin assignments of TVS parts.
摘要翻译： 公开了一种用于多个引脚分配的瞬态电压抑制器（TVS）。 抑制器包括彼此并联的至少两个级联二极管电路和与每个级联二极管电路并联并与低电压连接的静电放电钳位元件。 一个级联二极管电路与高电压连接，其他级联二极管电路分别与I / O引脚相连。 每个级联二极管电路还包括级联到第一二极管的第一二极管和第二二极管，其中第一二极管和第二二极管之间的节点与高电压或一个I / O引脚连接。 本发明的设计可以满足多个限制要求。 它是TVS零件的灵活不同的引脚分配。
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