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公开(公告)号：US20090002028A1
公开(公告)日：2009-01-01
申请号：US11769716
申请日：2007-06-28
申请人： Ming-Dou Ker , Hui-Wen Tsai , Ryan Hsin-Chin Jiang
发明人： Ming-Dou Ker , Hui-Wen Tsai , Ryan Hsin-Chin Jiang
IPC分类号： H03K19/0175
CPC分类号： H03K19/00315
摘要： A Mixed-voltage input and output (I/O) buffer including a pre-driver unit, a bulk-voltage generating unit, a first to a third transistors and an input stage unit is provided. The pre-driver unit outputs a first source/drain and a second signal. The bulk-voltage generating unit determines whether a first voltage or a pad voltage is used as a bulk voltage according to the pad voltage level. A gate of the first transistor receives the first signal, and a bulk, a first source/drain and a second source/drain of the first transistor are respectively coupled to the bulk voltage, the first voltage and the pad. A gate of the third transistor receives the second signal, and a first source/drain and a second source/drain of the third transistor are respectively coupled to the input stage unit for receiving an input signal from the pad and a second voltage.
摘要翻译： 提供了包括预驱动器单元，体电压产生单元，第一至第三晶体管和输入级单元的混合电压输入和输出（I / O）缓冲器。 预驱动器单元输出第一源极/漏极和第二信号。 体积电压产生单元根据焊盘电压电平来确定是否使用第一电压或焊盘电压作为体电压。 第一晶体管的栅极接收第一信号，并且第一晶体管的体，第一源极/漏极和第二源极/漏极分别耦合到体电压，第一电压和焊盘。 第三晶体管的栅极接收第二信号，第三晶体管的第一源极/漏极和第二源极/漏极分别耦合到输入级单元，用于从焊盘接收输入信号和第二电压。
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公开(公告)号：US20090135533A1
公开(公告)日：2009-05-28
申请号：US11987222
申请日：2007-11-28
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An ESD protection circuit including a clamping module and a detecting module is provided. The clamping module is coupled between a positive power line and a negative power line. The detecting module includes a triggering unit, a resistor, and a MOS capacitor. An output terminal of the triggering unit is used for triggering the clamping module. The resistor is coupled between the positive power line and an input terminal of the triggering unit. The MOS capacitor has a first end and a second end. The first end is coupled to the input terminal of the triggering unit. During a normal power operation, a switching terminal of the triggering unit enables the second end of the MOS capacitor to be coupled with the positive power line. Thereby, the gate tunneling leakage is eliminated and the problem of mistriggering is prevented.
摘要翻译： 提供了包括夹紧模块和检测模块的ESD保护电路。 夹紧模块耦合在正电源线和负电源线之间。 检测模块包括触发单元，电阻器和MOS电容器。 触发单元的输出端子用于触发夹紧模块。 电阻器耦合在正电源线和触发单元的输入端之间。 MOS电容器具有第一端和第二端。 第一端耦合到触发单元的输入端。 在正常电力操作期间，触发单元的开关端子使MOS电容器的第二端与正电源线耦合。 由此，消除了栅极隧道泄漏，并且防止了错误捕捉的问题。
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3.发明申请公开(公告)号：US20090009229A1
公开(公告)日：2009-01-08
申请号：US11773966
申请日：2007-07-06
IPC分类号： H03L5/00
CPC分类号： H03B5/36
摘要： A high/low voltage tolerant interface circuit and a crystal oscillator circuit using the same are provided herein. The interface circuit includes a first transistor, a bulk-voltage generator module and an bias module. The first transistor includes a gate, a first source/drain, a bulk coupled to the first source/drain of the first transistor and a second source/drain coupled to an input node. The bulk-voltage generator module is, used to determine whether a first voltage or a predetermined voltage is being provided to the bulk of the first transistor according to the voltage of the input node. The bias module is coupled to the gate of the first transistor. The bias module is used to provide an bias voltage to the gate of the first transistor and makes the first transistor conduct in order to control the voltage of the second source/drain voltage of the first transistor.
摘要翻译： 本文提供了高/低电压容限接口电路和使用其的晶体振荡器电路。 接口电路包括第一晶体管，体电压发生器模块和偏置模块。 第一晶体管包括栅极，第一源极/漏极，耦合到第一晶体管的第一源极/漏极的体，以及耦合到输入节点的第二源极/漏极。 大容量电压发生器模块用于根据输入节点的电压确定是否向第一晶体管本体提供第一电压或预定电压。 偏置模块耦合到第一晶体管的栅极。 偏置模块用于向第一晶体管的栅极提供偏置电压，并使第一晶体管导通，以便控制第一晶体管的第二源极/漏极电压的电压。
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4.发明授权公开(公告)号：US08829775B2
公开(公告)日：2014-09-09
申请号：US13464506
申请日：2012-05-04
CPC分类号： H01J9/02 , H01J17/066
摘要： The present invention discloses a semiconductor-based planar micro-tube discharger structure and a method for fabricating the same. The method comprises steps: forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap; forming an insulating layer over the patterned electrodes and the separating block and filling the insulating layer into the gap. Thereby are formed at least two discharge paths. The method can fabricate a plurality discharge paths in a semiconductor structure. Therefore, the structure of the present invention has very high reliability and reusability.
摘要翻译： 本发明公开了一种基于半导体的平面微管放电器结构及其制造方法。 该方法包括以下步骤：在衬底上形成由间隙分开的两个图案化电极和布置在间隙中的至少一个分隔块; 在图案化电极和分离块上形成绝缘层，并将绝缘层填充到间隙中。 由此形成至少两个排出路径。 该方法可以在半导体结构中制造多个放电路径。 因此，本发明的结构具有非常高的可靠性和可重用性。
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5.发明申请公开(公告)号：US20130221834A1
公开(公告)日：2013-08-29
申请号：US13464506
申请日：2012-05-04
CPC分类号： H01J9/02 , H01J17/066
摘要： The present invention discloses a semiconductor-based planar micro-tube discharger structure and a method for fabricating the same. The method comprises steps: forming on a substrate two patterned electrodes separated by a gap and at least one separating block arranged in the gap; forming an insulating layer over the patterned electrodes and the separating block and filling the insulating layer into the gap. Thereby are formed at least two discharge paths. The method can fabricate a plurality discharge paths in a semiconductor structure. Therefore, the structure of the present invention has very high reliability and reusability.
摘要翻译： 本发明公开了一种基于半导体的平面微管放电器结构及其制造方法。 该方法包括以下步骤：在衬底上形成由间隙分开的两个图案化电极和布置在间隙中的至少一个分隔块; 在图案化电极和分离块上形成绝缘层，并将绝缘层填充到间隙中。 由此形成至少两个排出路径。 该方法可以在半导体结构中制造多个放电路径。 因此，本发明的结构具有非常高的可靠性和可重用性。
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公开(公告)号：US07915638B2
公开(公告)日：2011-03-29
申请号：US12113912
申请日：2008-05-01
IPC分类号： H01L29/66
CPC分类号： H01L27/0262 , H01L29/747 , H01L29/87
摘要： The present invention discloses a symmetric bidirectional silicon-controlled rectifier, which comprises: a substrate; a buried layer formed on the substrate; a first well, a middle region and a second well, which are sequentially formed on the buried layer side-by-side; a first semiconductor area and a second semiconductor area both formed inside the first well; a third semiconductor area formed in a junction between the first well and the middle region, wherein a first gate is formed over a region between the second and third semiconductor areas; a fourth semiconductor area and a fifth semiconductor area both formed inside the second well; a sixth semiconductor area formed in a junction between the second well and the middle region, wherein a second gate is formed over a region between the fifth and sixth semiconductor areas.
摘要翻译： 本发明公开了一种对称双向硅控整流器，其包括：衬底; 形成在基板上的掩埋层; 第一阱，中间区域和第二阱，并排地依次形成在掩埋层上; 第一半导体区域和第二半导体区域都形成在第一阱内; 形成在所述第一阱和所述中间区域之间的接合处的第三半导体区域，其中在所述第二和第三半导体区域之间的区域上形成第一栅极; 形成在第二阱内的第四半导体区域和第五半导体区域; 形成在所述第二阱和所述中间区域之间的接合处的第六半导体区域，其中在所述第五和第六半导体区域之间的区域上形成第二栅极。
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公开(公告)号：US07817386B2
公开(公告)日：2010-10-19
申请号：US11907206
申请日：2007-10-10
IPC分类号： H02H9/00
CPC分类号： H01L27/0266 , H01L2924/0002 , H01L2924/00
摘要： An ESD protection circuit suitable for applying in an integrated circuit with separated power domains is provided. The circuit includes a P-type MOSFET coupled between a first circuit in a first power domain and a second circuit in a second power domain. A source terminal of the P-type MOSFET is coupled to a connection node for connecting the first circuit and the second circuit. A gate terminal of the P-type MOSFET is coupled to a positive power line of the second power domain. A drain terminal of the P-type MOSFET is coupled to a negative power line of the second power domain. A body terminal of the P-type MOSFET is also coupled to the connection node.
摘要翻译： 提供一种适用于具有分离电源域的集成电路中的ESD保护电路。 电路包括耦合在第一电源域中的第一电路和第二电源域中的第二电路之间的P型MOSFET。 P型MOSFET的源极端子连接到用于连接第一电路和第二电路的连接节点。 P型MOSFET的栅极端子耦合到第二电源域的正电源线。 P型MOSFET的漏极端子耦合到第二电源域的负电源线。 P型MOSFET的体式端子也耦合到连接节点。
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公开(公告)号：US07755871B2
公开(公告)日：2010-07-13
申请号：US11987222
申请日：2007-11-28
IPC分类号： H02H9/04
CPC分类号： H02H9/046
摘要： An ESD protection circuit including a clamping module and a detecting module is provided. The clamping module is coupled between a positive power line and a negative power line. The detecting module includes a triggering unit, a resistor, and a MOS capacitor. An output terminal of the triggering unit is used for triggering the clamping module. The resistor is coupled between the positive power line and an input terminal of the triggering unit. The MOS capacitor has a first end and a second end. The first end is coupled to the input terminal of the triggering unit. During a normal power operation, a switching terminal of the triggering unit enables the second end of the MOS capacitor to be coupled with the positive power line. Thereby, the gate tunneling leakage is eliminated and the problem of mistriggering is prevented.
摘要翻译： 提供了包括夹紧模块和检测模块的ESD保护电路。 夹紧模块耦合在正电源线和负电源线之间。 检测模块包括触发单元，电阻器和MOS电容器。 触发单元的输出端子用于触发夹紧模块。 电阻器耦合在正电源线和触发单元的输入端之间。 MOS电容器具有第一端和第二端。 第一端耦合到触发单元的输入端。 在正常电力操作期间，触发单元的开关端子使MOS电容器的第二端与正电源线耦合。 由此，消除了栅极隧道泄漏，并且防止了错误捕捉的问题。
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9.发明授权公开(公告)号：US07564317B2
公开(公告)日：2009-07-21
申请号：US11773966
申请日：2007-07-06
IPC分类号： H03B5/36
CPC分类号： H03B5/36
摘要： A high/low voltage tolerant interface circuit and a crystal oscillator circuit using the same are provided herein. The interface circuit includes a first transistor, a bulk-voltage generator module and an bias module. The first transistor includes a gate, a first source/drain, a bulk coupled to the first source/drain of the first transistor and a second source/drain coupled to an input node. The bulk-voltage generator module is, used to determine whether a first voltage or a predetermined voltage is being provided to the bulk of the first transistor according to the voltage of the input node. The bias module is coupled to the gate of the first transistor. The bias module is used to provide an bias voltage to the gate of the first transistor and makes the first transistor conduct in order to control the voltage of the second source/drain voltage of the first transistor.
摘要翻译： 本文提供了高/低电压容限接口电路和使用其的晶体振荡器电路。 接口电路包括第一晶体管，体电压发生器模块和偏置模块。 第一晶体管包括栅极，第一源极/漏极，耦合到第一晶体管的第一源极/漏极的体，以及耦合到输入节点的第二源极/漏极。 大容量电压发生器模块用于根据输入节点的电压确定是否向第一晶体管本体提供第一电压或预定电压。 偏置模块耦合到第一晶体管的栅极。 偏置模块用于向第一晶体管的栅极提供偏置电压，并使第一晶体管导通，以便控制第一晶体管的第二源极/漏极电压的电压。
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公开(公告)号：US20090032838A1
公开(公告)日：2009-02-05
申请号：US12113912
申请日：2008-05-01
IPC分类号： H01L29/747
CPC分类号： H01L27/0262 , H01L29/747 , H01L29/87
摘要： The present invention discloses a symmetric bidirectional silicon-controlled rectifier, which comprises: a substrate; a buried layer formed on the substrate; a first well, a middle region and a second well, which are sequentially formed on the buried layer side-by-side; a first semiconductor area and a second semiconductor area both formed inside the first well; a third semiconductor area formed in a junction between the first well and the middle region, wherein a first gate is formed over a region between the second and third semiconductor areas; a fourth semiconductor area and a fifth semiconductor area both formed inside the second well; a sixth semiconductor area formed in a junction between the second well and the middle region, wherein a second gate is formed over a region between the fifth and sixth semiconductor areas.
摘要翻译： 本发明公开了一种对称双向硅控整流器，其包括：衬底; 形成在基板上的掩埋层; 第一阱，中间区域和第二阱，并排地依次形成在掩埋层上; 第一半导体区域和第二半导体区域都形成在第一阱内; 形成在所述第一阱和所述中间区域之间的接合处的第三半导体区域，其中在所述第二和第三半导体区域之间的区域上形成第一栅极; 形成在第二阱内的第四半导体区域和第五半导体区域; 形成在所述第二阱和所述中间区域之间的接合处的第六半导体区域，其中在所述第五和第六半导体区域之间的区域上形成第二栅极。
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