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公开(公告)号：US20120018778A1
公开(公告)日：2012-01-26
申请号：US12840749
申请日：2010-07-21
IPC分类号： H01L27/06
CPC分类号： H01L27/0259
摘要： A new ESD protection device with an integrated-circuit vertical transistor structure is disclosed, which includes a heavily doped p-type substrate (P+ substrate), a n-type well (N well) in the P+ substrate, a heavily doped p-type diffusion (P+ diffusion) in the N well, a heavily doped n-type diffusion (N+ diffusion) in the N well, and a p-type well (P well) surrounding the N well in the P+ substrate. A bond pad is connected to both the P+ and N+ diffusions, and a ground is coupled to the P+ substrate. Another P+ diffusion is implanted in the N well or another N+ diffusion is implanted in the P well to form a Zener diode, which behaves as a trigger for the PNP transistor when a positive ESD zaps. A parasitic diode is formed at the junction between the P+ substrate and the N well, to bypass a negative ESD stress on the bond pad.
摘要翻译： 公开了一种具有集成电路垂直晶体管结构的新型ESD保护器件，其包括重掺杂p型衬底（P +衬底），P +衬底中的n型阱（N阱），重掺杂p型衬底 N阱中的扩散（P +扩散），N阱中的重掺杂n型扩散（N +扩散）以及P +衬底中N阱周围的p型阱（P阱）。 接合焊盘连接到P +和N +扩散两者，并且接地耦合到P +衬底。 将另一个P +扩散注入到N阱中，或者将另一个N +扩散注入到P阱中以形成齐纳二极管，当正ESD成像时，其作为PNP晶体管的触发器。 在P +衬底和N阱之间的接合处形成寄生二极管，以绕过接合焊盘上的负ESD应力。
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公开(公告)号：US08217421B2
公开(公告)日：2012-07-10
申请号：US12840749
申请日：2010-07-21
IPC分类号： H01L29/66
CPC分类号： H01L27/0259
摘要： A new ESD protection device with an integrated-circuit vertical transistor structure is disclosed, which includes a heavily doped p-type substrate (P+ substrate), a n-type well (N well) in the P+ substrate, a heavily doped p-type diffusion (P+ diffusion) in the N well, a heavily doped n-type diffusion (N+ diffusion) in the N well, and a p-type well (P well) surrounding the N well in the P+ substrate. A bond pad is connected to both the P+ and N+ diffusions, and a ground is coupled to the P+ substrate. Another P+ diffusion is implanted in the N well or another N+ diffusion is implanted in the P well to form a Zener diode, which behaves as a trigger for the PNP transistor when a positive ESD zaps. A parasitic diode is formed at the junction between the P+ substrate and the N well, to bypass a negative ESD stress on the bond pad.
摘要翻译： 公开了一种具有集成电路垂直晶体管结构的新型ESD保护器件，其包括重掺杂p型衬底（P +衬底），P +衬底中的n型阱（N阱），重掺杂p型衬底 N阱中的扩散（P +扩散），N阱中的重掺杂n型扩散（N +扩散）以及P +衬底中N阱周围的p型阱（P阱）。 接合焊盘连接到P +和N +扩散两者，并且接地耦合到P +衬底。 将另一个P +扩散注入到N阱中，或者将另一个N +扩散注入到P阱中以形成齐纳二极管，当正ESD成像时，其作为PNP晶体管的触发器。 在P +衬底和N阱之间的接合处形成寄生二极管，以绕过接合焊盘上的负ESD应力。
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公开(公告)号：US08552530B2
公开(公告)日：2013-10-08
申请号：US12848531
申请日：2010-08-02
IPC分类号： H01L29/06
CPC分类号： H01L27/0259
摘要： A vertical transient voltage suppressor for protecting an electronic device is disclosed. The vertical transient voltage includes a conductivity type substrate having highly doping concentration; a first type lightly doped region is arranged on the conductivity type substrate, wherein the conductivity type substrate and the first type lightly doped region respectively belong to opposite types; a first type heavily doped region and a second type heavily doped region are arranged in the first type lightly doped region, wherein the first and second type heavily doped regions and the conductivity type substrate belong to same types; and a deep first type heavily doped region is arranged on the conductivity type substrate and neighbors the first type lightly doped region, wherein the deep first type heavily doped region and the first type lightly doped region respectively belong to opposite types, and wherein the deep first type heavily doped region is coupled to the first type heavily doped region.
摘要翻译： 公开了一种用于保护电子设备的垂直瞬态电压抑制器。 垂直瞬变电压包括具有高掺杂浓度的导电型衬底; 导电型衬底上布置有第一类型轻掺杂区域，其中导电类型衬底和第一类型轻掺杂区域分别属于相反类型; 第一类型重掺杂区和第二类重掺杂区布置在第一类型轻掺杂区域中，其中第一和第二类型重掺杂区和导电类型衬底属于相同类型; 并且深度第一类型重掺杂区域布置在导电类型衬底上并且与第一类型轻掺杂区域相邻，其中深第一类型重掺杂区域和第一类型轻掺杂区域分别属于相反类型，并且其中深第一类型重掺杂区域 型重掺杂区域耦合到第一类型重掺杂区域。
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公开(公告)号：US08304838B1
公开(公告)日：2012-11-06
申请号：US13216016
申请日：2011-08-23
IPC分类号： H01L21/00
CPC分类号： H01L27/0255
摘要： An electrostatic discharge protection device structure is disclosed, which comprises a semiconductor substrate and an N-type epitaxial layer arranged on the semiconductor substrate. At least one snapback cascade structure is arranged in the N-type epitaxial layer, wherein the snapback cascade structure further comprises first and second P-type wells arranged in the N-type epitaxial layer. First and second heavily doped areas arranged in the first P-type well respectively belong to opposite types. And, third and fourth heavily doped areas arranged in the second P-type well respectively belong to opposite types, wherein the second and third heavily doped areas respectively belong to opposite types and are electrically connected with each other. When the first heavily doped area receives an ESD signal, an ESD current flows from the first heavily doped area to the fourth heavily doped area through the first P-type well, the N-type epitaxial layer, and the second P-type well.
摘要翻译： 公开了一种静电放电保护器件结构，其包括半导体衬底和布置在半导体衬底上的N型外延层。 在N型外延层中布置有至少一个快速反应级联结构，其中快速回退级联结构还包括布置在N型外延层中的第一和第二P型阱。 排列在第一P型井中的第一和第二重掺杂区域分别属于相反的类型。 并且，排列在第二P型阱中的第三和第四重掺杂区域分别属于相反的类型，其中第二和第三重掺杂区域分别属于相反的类型并且彼此电连接。 当第一重掺杂区域接收到ESD信号时，ESD电流通过第一P型阱，N型外延层和第二P型阱从第一重掺杂区流动到第四重掺杂区。
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公开(公告)号：US20130153957A1
公开(公告)日：2013-06-20
申请号：US13331241
申请日：2011-12-20
IPC分类号： H01L29/73
CPC分类号： H01L27/0262 , H01L29/861
摘要： A silicon-controlled-rectifier (SCR) with adjustable holding voltage is disclosed, which comprises a heavily doped semiconductor layer and an epitaxial layer formed on the heavily doped semiconductor layer. A first N-well having a first P-heavily doped area is formed in the epitaxial layer. A second N-well or a first P-well is formed in the epitaxial layer. When the second N-well is formed in the epitaxial layer, a P-doped area is located between the first N-well and the second N-well. Besides, a first N-heavily doped area is formed in the second N-well or the first P-well. At least one deep isolation trench is formed in the epitaxial layer and located between the first P-heavily doped area and the first N-heavily doped area. A distance between the deep isolation trench and the heavily doped semiconductor layer is larger than zero.
摘要翻译： 公开了具有可调保持电压的硅控整流器（SCR），其包括在重掺杂半导体层上形成的重掺杂半导体层和外延层。 在外延层中形成具有第一P重掺杂区的第一N阱。 在外延层中形成第二N阱或第一P阱。 当第二N阱形成在外延层中时，P掺杂区域位于第一N阱和第二N阱之间。 此外，在第二N阱或第一P阱中形成第一N重掺杂区。 在外延层中形成至少一个深的隔离沟槽，并且位于第一P重掺杂区域和第一N重掺杂区域之间。 深隔离沟槽和重掺杂半导体层之间的距离大于零。
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公开(公告)号：US20130127007A1
公开(公告)日：2013-05-23
申请号：US13303946
申请日：2011-11-23
IPC分类号： H01L29/06
CPC分类号： H01L27/0296 , H01L29/8613 , H01L29/866
摘要： A transient voltage suppressor without leakage current is disclosed, which comprises a P-substrate. There is an N-type epitaxial layer formed on the P-substrate, and a first N-heavily doped area, a first P-heavily doped area, an electrostatic discharge (ESD) device and at least one deep isolation trench are formed in the N-epitaxial layer. A first N-buried area is formed in the bottom of the N-epitaxial layer to neighbor the P-substrate and located below the first N-heavily doped area and the first P-heavily doped area. The ESD device is coupled to the first N-heavily doped area. The deep isolation trench is not only adjacent to the first N-heavily doped area, but has a depth greater than a depth of the first N-buried area, thereby separating the first N-buried area and the ESD device.
摘要翻译： 公开了一种无泄漏电流的瞬态电压抑制器，其包括P型衬底。 在P基板上形成有N型外延层，在第一N重掺杂区，第一P重掺杂区，静电放电（ESD）器件和至少一个深隔离沟槽中形成第一N重掺杂区， N外延层。 在N外延层的底部形成第一N区，以邻近P衬底并且位于第一N重掺杂区和第一P重掺杂区的下方。 ESD器件耦合到第一N重掺杂区域。 深隔离沟槽不仅与第一N重掺杂区相邻，而且具有大于第一N埋入区深度的深度，从而分离第一N埋区和ESD器。
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公开(公告)号：US20120241903A1
公开(公告)日：2012-09-27
申请号：US13072138
申请日：2011-03-25
IPC分类号： H01L29/66
CPC分类号： H01L27/0255 , H01L29/861
摘要： A low capacitance transient voltage suppressor is disclosed. The suppressor comprises an N-type heavily doped substrate and an epitaxial layer formed on the substrate. At least one steering diode structure formed in the epitaxial layer comprises a diode lightly doped well and a first P-type lightly doped well, wherein a P-type heavily doped area is formed in the diode lightly doped well and a first N-type heavily doped area and a second P-type heavily doped area are formed in the first P-type lightly doped well. A second P-type lightly doped well having two N-type heavily doped areas is formed in the epitaxial layer. In addition, an N-type heavily doped well and at least one deep isolation trench are formed in the epitaxial layer, wherein the trench has a depth greater than or equal to depths of all the doped wells, so as to separate at least one doped well.
摘要翻译： 公开了一种低电容瞬态电压抑制器。 抑制器包括N型重掺杂衬底和形成在衬底上的外延层。 形成在外延层中的至少一个转向二极管结构包括二极管轻掺杂阱和第一P型轻掺杂阱，其中在二极管轻掺杂阱中形成P型重掺杂区，并且第一N型重掺杂阱 在第一P型轻掺杂阱中形成掺杂区域和第二P型重掺杂区域。 在外延层中形成具有两个N型重掺杂区的第二P型轻掺杂阱。 此外，在外延层中形成N型重掺杂阱和至少一个深隔离沟槽，其中沟槽的深度大于或等于所有掺杂阱的深度，以便分离至少一个掺杂的 好。
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公开(公告)号：US20120014027A1
公开(公告)日：2012-01-19
申请号：US12836745
申请日：2010-07-15
IPC分类号： H02H3/22
CPC分类号： H02H9/046 , H05K1/0259
摘要： A transient voltage suppressor (TVS) for multiple pin assignments is disclosed. The suppressor comprises at least two cascade-diode circuits in parallel to each other and an electrostatic-discharge clamp element in parallel to each cascade-diode circuit and connected with a low voltage. One cascade-diode circuit is connected with a high voltage, and the other cascade-diode circuits are respectively connected with I/O pins. Each cascade-diode circuit further comprises a first diode and a second diode cascaded to the first diode, wherein a node between the first diode and the second diode is connected with the high voltage or the one I/O pin. The design of the present invention can meet several bounding requirements. It is flexible different pin assignments of TVS parts.
摘要翻译： 公开了一种用于多个引脚分配的瞬态电压抑制器（TVS）。 抑制器包括彼此并联的至少两个级联二极管电路和与每个级联二极管电路并联并与低电压连接的静电放电钳位元件。 一个级联二极管电路与高电压连接，其他级联二极管电路分别与I / O引脚相连。 每个级联二极管电路还包括级联到第一二极管的第一二极管和第二二极管，其中第一二极管和第二二极管之间的节点与高电压或一个I / O引脚连接。 本发明的设计可以满足多个限制要求。 它是TVS零件的灵活不同的引脚分配。
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公开(公告)号：US08785971B2
公开(公告)日：2014-07-22
申请号：US13303946
申请日：2011-11-23
IPC分类号： H01L23/58 , H01L27/02 , H01L29/866 , H01L29/861
CPC分类号： H01L27/0296 , H01L29/8613 , H01L29/866
摘要： A transient voltage suppressor without leakage current is disclosed, which comprises a P-substrate. There is an N-type epitaxial layer formed on the P-substrate, and a first N-heavily doped area, a first P-heavily doped area, an electrostatic discharge (ESD) device and at least one deep isolation trench are formed in the N-epitaxial layer. A first N-buried area is formed in the bottom of the N-epitaxial layer to neighbor the P-substrate and located below the first N-heavily doped area and the first P-heavily doped area. The ESD device is coupled to the first N-heavily doped area. The deep isolation trench is not only adjacent to the first N-heavily doped area, but has a depth greater than a depth of the first N-buried area, thereby separating the first N-buried area and the ESD device.
摘要翻译： 公开了一种无泄漏电流的瞬态电压抑制器，其包括P型衬底。 在P基板上形成有N型外延层，在第一N重掺杂区，第一P重掺杂区，静电放电（ESD）器件和至少一个深隔离沟槽中形成第一N重掺杂区， N外延层。 在N外延层的底部形成第一N区，以邻近P衬底并且位于第一N重掺杂区和第一P重掺杂区的下方。 ESD器件耦合到第一N重掺杂区域。 深隔离沟槽不仅与第一N重掺杂区相邻，而且具有大于第一N埋入区深度的深度，从而分离第一N埋区和ESD器。
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公开(公告)号：US08169000B2
公开(公告)日：2012-05-01
申请号：US12836785
申请日：2010-07-15
IPC分类号： H01L23/62
CPC分类号： H01L27/0255
摘要： A lateral transient voltage suppressor with ultra low capacitance is disclosed. The suppressor comprises a first conductivity type substrate and at least one diode cascade structure arranged in the first conductivity type substrate. The cascade structure further comprises at least one second conductivity type lightly doped well and at least one first conductivity type lightly doped well, wherein there are two heavily doped areas arranged in the second conductivity type lightly doped well and the first conductivity type lightly doped well. The cascade structure neighbors a second conductivity type well, wherein there are three heavily doped areas arranged in the second conductivity type well. The suppressor further comprises a plurality of deep isolation trenches arranged in the first conductivity type substrate and having a depth greater than depths of the second conductivity type lightly doped well, the second conductivity type well and the first conductivity type lightly doped well. Each doped well is isolated by trenches.
摘要翻译： 公开了具有超低电容的横向瞬态电压抑制器。 抑制器包括第一导电型衬底和布置在第一导电类型衬底中的至少一个二极管级联结构。 级联结构还包括至少一个第二导电类型轻掺杂阱和至少一个第一导电类型轻掺杂阱，其中存在布置在第二导电类型轻掺杂阱和第一导电类型轻掺杂阱中的两个重掺杂区。 级联结构邻近第二导电类型阱，其中存在布置在第二导电类型阱中的三个重掺杂区域。 抑制器还包括布置在第一导电类型衬底中并且具有大于第二导电类型轻掺杂阱的深度的深度的多个深隔离沟槽，第二导电类型阱和第一导电类型轻掺杂阱。 每个掺杂的阱由沟槽隔离。
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