公开(公告)号：US20120025350A1

公开(公告)日：2012-02-02

申请号：US12848531

申请日：2010-08-02

申请人： Kun-Hsien LIN ,  Zi-Ping CHEN ,  Che-Hao CHUANG ,  Ryan Hsin-Chin JIANG

发明人： Kun-Hsien LIN ,  Zi-Ping CHEN ,  Che-Hao CHUANG ,  Ryan Hsin-Chin JIANG

IPC分类号： H01L29/06

CPC分类号： H01L27/0259

摘要： A vertical transient voltage suppressor for protecting an electronic device is disclosed. The vertical transient voltage includes a conductivity type substrate having highly doping concentration; a first type lightly doped region is arranged on the conductivity type substrate, wherein the conductivity type substrate and the first type lightly doped region respectively belong to opposite types; a first type heavily doped region and a second type heavily doped region are arranged in the first type lightly doped region, wherein the first and second type heavily doped regions and the conductivity type substrate belong to same types; and a deep first type heavily doped region is arranged on the conductivity type substrate and neighbors the first type lightly doped region, wherein the deep first type heavily doped region and the first type lightly doped region respectively belong to opposite types, and wherein the deep first type heavily doped region is coupled to the first type heavily doped region.

摘要翻译： 公开了一种用于保护电子设备的垂直瞬态电压抑制器。 垂直瞬变电压包括具有高掺杂浓度的导电型衬底; 导电型衬底上布置有第一类型轻掺杂区域，其中导电类型衬底和第一类型轻掺杂区域分别属于相反类型; 第一类型重掺杂区和第二类重掺杂区布置在第一类型轻掺杂区域中，其中第一和第二类型重掺杂区和导电类型衬底属于相同类型; 并且深度第一类型重掺杂区域布置在导电类型衬底上并且与第一类型轻掺杂区域相邻，其中深第一类型重掺杂区域和第一类型轻掺杂区域分别属于相反类型，并且其中深第一类型重掺杂区域 型重掺杂区域耦合到第一类型重掺杂区域。

公开(公告)号：US20120014027A1

公开(公告)日：2012-01-19

申请号：US12836745

申请日：2010-07-15

申请人： Kun-Hsien LIN ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang

发明人： Kun-Hsien LIN ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang

IPC分类号： H02H3/22

CPC分类号： H02H9/046 ,  H05K1/0259

摘要： A transient voltage suppressor (TVS) for multiple pin assignments is disclosed. The suppressor comprises at least two cascade-diode circuits in parallel to each other and an electrostatic-discharge clamp element in parallel to each cascade-diode circuit and connected with a low voltage. One cascade-diode circuit is connected with a high voltage, and the other cascade-diode circuits are respectively connected with I/O pins. Each cascade-diode circuit further comprises a first diode and a second diode cascaded to the first diode, wherein a node between the first diode and the second diode is connected with the high voltage or the one I/O pin. The design of the present invention can meet several bounding requirements. It is flexible different pin assignments of TVS parts.

摘要翻译： 公开了一种用于多个引脚分配的瞬态电压抑制器（TVS）。 抑制器包括彼此并联的至少两个级联二极管电路和与每个级联二极管电路并联并与低电压连接的静电放电钳位元件。 一个级联二极管电路与高电压连接，其他级联二极管电路分别与I / O引脚相连。 每个级联二极管电路还包括级联到第一二极管的第一二极管和第二二极管，其中第一二极管和第二二极管之间的节点与高电压或一个I / O引脚连接。 本发明的设计可以满足多个限制要求。 它是TVS零件的灵活不同的引脚分配。

公开(公告)号：US20130003242A1

公开(公告)日：2013-01-03

申请号：US13612253

申请日：2012-09-12

申请人： Kun-Hsien LIN ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang

发明人： Kun-Hsien LIN ,  Che-Hao Chuang ,  Ryan Hsin-Chin Jiang

IPC分类号： H02H3/22

CPC分类号： H02H9/046 ,  H05K1/0259

摘要： A transient voltage suppressor (TVS) for multiple pin assignments is disclosed. The suppressor comprises at least two cascade-diode circuits in parallel to each other and an electrostatic-discharge clamp element in parallel to each cascade-diode circuit and connected with a low voltage.One cascade-diode circuit is connected with a high voltage, and the other cascade-diode circuits are respectively connected with I/O pins. Each cascade-diode circuit further comprises a first diode and a second diode cascaded to the first diode, wherein a node between the first diode and the second diode is connected with the high voltage or the one I/O pin. The design of the present invention can meet several bounding requirements. It is flexible different pin assignments of TVS parts.

摘要翻译： 公开了一种用于多个引脚分配的瞬态电压抑制器（TVS）。 抑制器包括彼此并联的至少两个级联二极管电路和与每个级联二极管电路并联并与低电压连接的静电放电钳位元件。 一个级联二极管电路与高电压连接，其他级联二极管电路分别与I / O引脚相连。 每个级联二极管电路还包括级联到第一二极管的第一二极管和第二二极管，其中第一二极管和第二二极管之间的节点与高电压或一个I / O引脚连接。 本发明的设计可以满足多个限制要求。 它是TVS零件的灵活不同的引脚分配。

公开(公告)号：US20120273902A1

公开(公告)日：2012-11-01

申请号：US13094953

申请日：2011-04-27

申请人： Kun-Hsien LIN ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chun-Yuan Wu

发明人： Kun-Hsien LIN ,  Hsin-Fu Huang ,  Chi-Mao Hsu ,  Chin-Fu Lin ,  Chun-Yuan Wu

IPC分类号： H01L29/772 ,  H01L21/28

CPC分类号： H01L21/31144 ,  H01L21/28008 ,  H01L29/401 ,  H01L29/4966 ,  H01L29/66545 ,  H01L29/78

摘要： A gate stack structure with an etch stop layer is provided. The gate stack structure is formed over a substrate. A spacer is formed on a sidewall of the gate stack structure. The gate stack structure includes a gate dielectric layer, a barrier layer, a repair layer and the etch stop layer. The gate dielectric layer is formed on the substrate. The barrier layer is formed on the gate dielectric layer. The barrier layer and an inner sidewall of the spacer collectively define a trench. The repair layer is formed on the barrier layer and an inner wall of the trench. The etch stop layer is formed on the repair layer.

摘要翻译： 提供具有蚀刻停止层的栅极堆叠结构。 栅极堆叠结构形成在衬底上。 在栅堆叠结构的侧壁上形成间隔物。 栅极堆叠结构包括栅极介电层，阻挡层，修复层和蚀刻停止层。 栅极电介质层形成在基板上。 阻挡层形成在栅介质层上。 隔离层和间隔物的内侧壁共同限定沟槽。 修复层形成在阻挡层和沟槽的内壁上。 蚀刻停止层形成在修复层上。