公开(公告)号：US20100072821A1

公开(公告)日：2010-03-25

申请号：US12507660

申请日：2009-07-22

申请人： Kenichiro YAMAGUCHI ,  Atsushi Okumura ,  Mitsugu Kusunoki ,  Tomoo Murata

发明人： Kenichiro YAMAGUCHI ,  Atsushi Okumura ,  Mitsugu Kusunoki ,  Tomoo Murata

IPC分类号： H02J3/00

CPC分类号： H03M1/0643 ,  H01L27/0203 ,  H03M1/687 ,  H03M1/745 ,  H03M1/785 ,  Y10T307/696

摘要： Operating speed as well as output accuracy of a D-A converter is enhanced. With a semiconductor device including unit current sources, and unit current source switches, plural current source elements constituting each of the unit current sources are disposed so as to be evenly dispersed, thereby reducing errors of the current source element, dependent on distance while the unit current source switches are concentratedly disposed in a small region, thereby mitigating delay in operation, attributable to parasitic capacitance. In addition, with the semiconductor device including R2R resistance ladders, the R2R resistance ladder is provided on the positive and the negative of each of the unit current source switches, and the respective R2R resistance ladders are shorted with each other at respective nodes on a unit current source switch-by-unit current source switch basis, are rendered identical in length, thereby cancelling out a nonlinearity error attributable to wiring parasitic resistance.

摘要翻译： 提高了D-A转换器的工作速度和输出精度。 利用包括单位电流源和单位电流源开关的半导体器件，构成每个单位电流源的多个电流源元件被布置成均匀分散，从而根据距离减小电流源元件的误差，而单元 电流源开关集中地设置在较小的区域中，从而减轻了由寄生电容引起的工作延迟。 另外，对于包含R2R电阻梯的半导体装置，在每个单位电流源开关的正极和负极上设置R2R电阻梯，并且相应的R2R电阻梯在单元的相应节点处相互短路 电流源逐个电流源开关基础的长度相同，从而消除归因于布线寄生电阻的非线性误差。

公开(公告)号：US07629669B2

公开(公告)日：2009-12-08

申请号：US11411096

申请日：2006-04-26

申请人： Koji Ishikawa ,  Kazutaka Mori ,  Hiroshige Kogayu ,  Tamotsu Miyake ,  Mitsugu Kusunoki

发明人： Koji Ishikawa ,  Kazutaka Mori ,  Hiroshige Kogayu ,  Tamotsu Miyake ,  Mitsugu Kusunoki

IPC分类号： H01L27/102

CPC分类号： H01L23/5252 ,  H01L27/0823 ,  H01L2924/0002 ,  H01L2924/00

摘要： A semiconductor apparatus includes a first transistor having a first emitter electrode, a first base electrode, and a first collector electrode in a region over a first region. Base lead-out polysilicon connecting the first base electrode and a first base region passes over a second region provided out of the first region and a resistor element is added. A writing voltage is reduced in an antifuse using two bipolar transistors.

摘要翻译： 半导体装置包括在第一区域的区域中具有第一发射极，第一基极和第一集电极的第一晶体管。 连接第一基极和第一基极区域的基极引出多晶硅通过在第一区域外提供的第二区域，并且添加电阻元件。 使用两个双极晶体管在反熔丝中减小写入电压。

公开(公告)号：US07522083B2

公开(公告)日：2009-04-21

申请号：US11877561

申请日：2007-10-23

申请人： Ryusuke Sahara ,  Mitsugu Kusunoki ,  Kazutaka Mori ,  Hiroshige Kogayu

发明人： Ryusuke Sahara ,  Mitsugu Kusunoki ,  Kazutaka Mori ,  Hiroshige Kogayu

IPC分类号： H03M1/78

CPC分类号： H03M1/1061 ,  H03M1/687 ,  H03M1/785 ,  H03M1/808

摘要： A DAC having a memory mat including a plurality of first memory cells, and a plurality of output lines connected to the plurality of first memory cells. Each of the plurality of memory cells has a first memory portion including bipolar transistors and storing information in non-volatility based on whether a junction of the bipolar transistors is destroyed or not, and a second memory portion connected to the first memory portion and for outputting information to corresponding one of the plurality of output lines. The DAC has a first mode in which information is transferred from the first memory portions to the second memory portions when the information is written into the second memory portions, and a second mode in which the second memory portions are specified externally and information is written into the second memory portions. Thus, the performance of a D/A converter can be improved.

摘要翻译： 具有包括多个第一存储单元的存储器垫的DAC和连接到多个第一存储单元的多个输出线。 多个存储单元中的每一个具有包括双极晶体管的第一存储器部分，并且基于双极晶体管的结是否被破坏来存储非易失性的信息，以及连接到第一存储器部分并用于输出的第二存储器部分 信息到多个输出行中的相应一个。 DAC具有第一模式，其中当信息被写入第二存储器部分时，信息从第一存储器部分传送到第二存储器部分，以及第二模式，其中第二存储器部分被外部指定并且信息被写入 第二存储器部分。 因此，可以提高D / A转换器的性能。

公开(公告)号：US06621352B2

公开(公告)日：2003-09-16

申请号：US09983968

申请日：2001-10-26

申请人： Takashi Matsumoto ,  Hikaru Suzuki ,  Mitsugu Kusunoki

发明人： Takashi Matsumoto ,  Hikaru Suzuki ,  Mitsugu Kusunoki

IPC分类号： H03L700

CPC分类号： G01R31/31709 ,  G01R31/31725 ,  G11C29/14 ,  H03K2005/00058 ,  H03L7/06 ,  H03L7/0814 ,  H03L7/095 ,  Y10S331/02

摘要： There is provided a semiconductor integrated circuit device for realizing in the higher accuracy the verification of a plurality of operations of a clock generation circuit to form an internal clock signal and enabling verification for various performances of the internal clock signal generation circuit while simplifying the structure thereof. In such semiconductor integrated circuit device, a measuring circuit for conducting at least two kinds of measurements among the measurements of lock time until the predetermined internal clock signal corresponding to the input clock signal can be obtained, the maximum frequency of the internal clock signal and jitter of the internal clock signal is provided to the clock generation circuit to form the internal clock signal corresponding to the input clock signal inputted from an external terminal. Thereby, operations of the clock generation circuit can be verified with higher accuracy within the semiconductor integrated circuit device.