公开(公告)号：US10725486B2

公开(公告)日：2020-07-28

申请号：US16052654

申请日：2018-08-02

Applicant: Novatek Microelectronics Corp.

Inventor： Yong-Ren Fang ,  Shen-Iuan Liu ,  Ju-Lin Huang ,  Tzu-Chien Tzeng ,  Keko-Chun Liang ,  Yu-Hsiang Wang ,  Che-Wei Yeh

IPC: G05F1/46 ,  H03K5/24 ,  G01R19/165

Abstract: A reference voltage generator includes a detecting voltage provider, a comparator, and a core circuit. The detecting voltage provider provides a detecting voltage with a first voltage level corresponding to a voltage coefficient. The comparator compares the first voltage level of the detecting voltage with a plurality of sampled amplitudes of an input signal to respectively generate a plurality of comparison results. The core circuit is used to: collect a plurality of first comparison results associated with a current received bit of a preset value from the comparison results; take the voltage coefficient as a first boundary voltage coefficient in response to the first comparison results satisfying a first condition; take the voltage coefficient as a second boundary voltage coefficient in response to the first comparison results satisfying a second condition. The reference circuit generates a reference voltage according to the first and second boundary voltage coefficients.

公开(公告)号：US11824966B2

公开(公告)日：2023-11-21

申请号：US17163527

申请日：2021-01-31

Applicant: NOVATEK Microelectronics Corp.

Inventor： Yong-Ren Fang ,  Yu-Hsiang Wang ,  Che-Wei Yeh

IPC: H04L7/04 ,  H04L7/027

CPC classification number: H04L7/027

Abstract: A transmitter is configured to transmit a series of command signals and a series of data signals. The transmitter includes a serializer and a multiplexer. The serializer is configured to generate the series of data signals. The multiplexer, coupled to the serializer, is configured to selectively output the series of command signals or the series of data signals.

公开(公告)号：US20230005451A1

公开(公告)日：2023-01-05

申请号：US17945082

申请日：2022-09-14

Applicant: NOVATEK Microelectronics Corp.

Inventor： Che-Wei Yeh ,  Keko-Chun Liang ,  Yu-Hsiang Wang ,  Yong-Ren Fang ,  Yi-Chuan Liu ,  Yi-Yang Tsai ,  Po-Hsiang Fang

IPC: G09G5/12

Abstract: A control system includes a plurality of driving circuits coupled in series, which include a first driving circuit and a second driving circuit. The first driving circuit includes a first receiver, a first transmitter and a first flag signal selector. The first transmitter is coupled to the first receiver, and the first flag signal selector is coupled between the first receiver and the first transmitter. The second driving circuit, coupled to the first driving circuit, includes a second receiver, a second transmitter and a second flag signal selector. The second transmitter is coupled to the second receiver, and the second flag signal selector is coupled between the second receiver and the second transmitter.

公开(公告)号：US11545081B2

公开(公告)日：2023-01-03

申请号：US17721337

申请日：2022-04-14

Applicant: Novatek Microelectronics Corp.

Inventor： Che-Wei Yeh ,  Keko-Chun Liang ,  Yu-Hsiang Wang ,  Yong-Ren Fang ,  Yi-Chuan Liu

IPC: G09G3/32

Abstract: A LED driving apparatus with clock embedded cascaded LED drivers is introduced, including: a plurality of LED drivers, wherein the first stage LED driver receives an original data signal and outputs a first data signal, the Nth stage LED driver receives a (N−1)th data signal and outputs a Nth data signal. The Nth stage LED driver includes a clock data recovery circuit generating a recovery clock signal and a recovery data signal according to the (N−1)th data signal; and a first transmitter outputting the Nth data signal according to the recovery clock signal and the recovery data signal.

公开(公告)号：US20220345123A1

公开(公告)日：2022-10-27

申请号：US17239671

申请日：2021-04-25

Applicant: NOVATEK Microelectronics Corp.

Inventor： Che-Wei Yeh ,  Keko-Chun Liang ,  Yu-Hsiang Wang ,  Yi-Chuan Liu

IPC: H03K5/156 ,  G06F1/06 ,  H03K5/135 ,  H03K5/00 ,  H03K5/133

Abstract: A clock generator includes a pulse generator and a duty cycle correction circuit. The pulse generator is configured to receive an input clock signal and generate a pulse signal according to the input clock signal. The duty cycle correction circuit, coupled to the pulse generator, is configured to adjust a duty cycle of the pulse signal to generate an output clock signal.

公开(公告)号：US11430382B2

公开(公告)日：2022-08-30

申请号：US17409824

申请日：2021-08-24

Applicant: Novatek Microelectronics Corp.

Inventor： Che-Wei Yeh ,  Keko-Chun Liang ,  Yu-Hsiang Wang ,  Po-Hsiang Fang ,  Ju-Lin Huang

IPC: G09G3/32

Abstract: A LED driving apparatus with differential signal interfaces is introduced, including: N-stages LED drivers, wherein the first stage LED driver receives a first data packet differential signal and a first clock differential signal and outputs a second data packet differential signal and a second clock differential signal, the Mth stage LED driver receives a Mth data packet differential signal and a Mth clock differential signal and outputs a (M+1)th data packet differential signal and a (M+1)th clock differential signal.

公开(公告)号：US11170702B2

公开(公告)日：2021-11-09

申请号：US17004025

申请日：2020-08-27

Applicant: Novatek Microelectronics Corp.

Inventor： Che-Wei Yeh ,  Keko-Chun Liang ,  Yu-Hsiang Wang ,  Po-Hsiang Fang ,  Ju-Lin Huang

IPC: G09G3/32

Abstract: A LED driving apparatus with differential signal interfaces is introduced, including: N-stages LED drivers, wherein the first stage LED driver receives a first data packet differential signal and a first clock differential signal and outputs a second data packet differential signal and a second clock differential signal, the Mth stage LED driver receives a Mth data packet differential signal and a Mth clock differential signal and outputs a (M+1)th data packet differential signal and a (M+1)th clock differential signal.

公开(公告)号：US11088818B1

公开(公告)日：2021-08-10

申请号：US16919049

申请日：2020-07-01

Applicant: NOVATEK Microelectronics Corp.

Inventor： Yong-Ren Fang ,  Yu-Hsiang Wang ,  Che-Wei Yeh

IPC: H04L7/04 ,  H04L7/027

Abstract: A receiver is configured to receive a series of command signals and a series of data signals. The receiver includes a first clock and data recovery (CDR) circuit, a control circuit and a second CDR circuit. The first CDR circuit is configured to process the series of command signal to generate a clock signal. The control circuit, coupled to the first CDR circuit, is configured to generate a control signal according to the series of command signals and the clock signal received from the first CDR circuit. The second CDR circuit, coupled to the control circuit, is configured to process the series of data signals according to the control signal received from the control circuit.

公开(公告)号：US20190243612A1

公开(公告)日：2019-08-08

申请号：US16159734

申请日：2018-10-15

Applicant: Novatek Microelectronics Corp.

Inventor： Che-Wei Yeh ,  Keko-Chun Liang ,  Yu-Hsiang Wang

IPC: G06F7/58 ,  H03K3/84 ,  H03M3/00

CPC classification number: G06F7/584 ,  H03K3/84 ,  H03M3/414

Abstract: A random bit stream generator which includes a pseudo-random bit stream generator and a multi-stage noise shaping (MASH) delta-sigma modulator is introduced. The pseudo-random bit stream generator may generate a first random bit stream according to a first clock signal. The MASH delta-sigma modulator is coupled to the first random bit stream generator to receive the first random bit stream and output a second random bit stream according to the first random bit stream and a second clock signal. A frequency of the second clock signal is greater than a frequency of the first clock signal, and the random bit stream has bell-shaped distribution. A method of generating a random bit stream having bell-shaped distribution adapted to a random bit stream generator is also introduced.