公开(公告)号：US20190146059A1

公开(公告)日：2019-05-16

申请号：US16119083

申请日：2018-08-31

Applicant: NXP B.V.

Inventor： Abdellatif Zanati ,  Jan-Peter Schat

IPC: G01S7/40 ,  H01Q3/26 ,  G01S13/02

Abstract: A built-in self-test, BIST, radar unit (100) is described. The BIST radar unit (100) comprises: a frequency generation circuit (110) configured to generate a mmW transmit signal; a transmitter circuit comprising: at least one phase shifter (130, 132) configured apply at least one phase shift to the mmW transmit signal; and at least one phase inverter (140, 142) coupled to the at least one phase shifter (130, 132) and configured to invert a phase of the phase shifted mmW transmit signal. A receiver configured to receive and process a received version of the mmW transmit signal. The at least one phase inverter (140, 142) is configured to rotate the phase shifted mmW transmit signal to apply a secondary modulation to the mmW transmit signal; and the receiver is configured to receive and process a received version of the mmW transmit signal to determine an operational state of the BIST radar unit (100) based on a determined phase shift performance of the secondary modulation of the received version of the mmW transmit signal.

公开(公告)号：US12035133B2

公开(公告)日：2024-07-09

申请号：US17301387

申请日：2021-04-01

Applicant: NXP B.V.

Inventor： Jan-Peter Schat

IPC: H04W12/041 ,  H04B1/04 ,  H04B1/16

CPC classification number: H04W12/041 ,  H04B1/04 ,  H04B1/16

Abstract: A communication device and method are provided for communicating data, such as a cryptographic key, wirelessly to another communication device. The communication device and the other device each include an oscillator circuit portion, an inverter, a non-inverting buffer, and a switch for switching between the inverter and non-inverting buffer. A circular loop is formed wirelessly between the oscillator circuit portions of both devices by placing both communication devices near each other. A control circuit in each device measures a parameter such as frequency or waveform pattern of the circulating signal to determine how to position the switches. The oscillator circuit portions may be portions of the same oscillator distributed between the devices, such as a delay line-controlled oscillator or a chaotic oscillator. Inverting and not inverting the circulated signal changes the parameter of the signal so that it is difficult for an eavesdropper to learn the communication.

公开(公告)号：US11943015B2

公开(公告)日：2024-03-26

申请号：US17449759

申请日：2021-10-01

Applicant: NXP B.V.

Inventor： Jan-Peter Schat

IPC: H04B7/06 ,  H04B7/0452

CPC classification number: H04B7/0452 ,  H04B7/0682

Abstract: A communications system (300) comprising: an antenna (320) that comprises a plurality of serially connected sub-antenna elements (322); and a signal generator (324) configured to provide a transmission signal to the antenna (320) for propagating along the sub-antenna elements (322). The transmission signal comprises a plurality of serial symbol packets. The signal generator (324) is configured to set the phase of the serial symbol packets such that when they align with predefined ones of the sub-antenna elements (322) the antenna (322) provides a beamformed signal.

公开(公告)号：US11693966B2

公开(公告)日：2023-07-04

申请号：US16540904

申请日：2019-08-14

Applicant: NXP B.V.

Inventor： Jan-Peter Schat

IPC: G06F21/56 ,  G06F21/55 ,  G01R31/317

CPC classification number: G06F21/567 ,  G06F21/552 ,  G06F21/554 ,  G06F21/566 ,  G01R31/31724 ,  G06F2221/034

Abstract: A method for managing operation of a circuit includes activating a trigger engine, receiving signals from a target circuit, and detecting a hardware trojan based on the signals. The trigger engine may generate a stimulus to activate the hardware trojan, and the target circuit may generate the received signals when the stimulus is generated. The trigger engine may be a scan chain which performs a circular scan by shifting bit values through a series of flip-flops including a feedback path. The target circuit may be various types of circuits, including but not limited to a high-speed input/output interface. The hardware trojan may be detected based on bit-error rate information corresponding to the signals output from the target circuit.

公开(公告)号：US11509461B2

公开(公告)日：2022-11-22

申请号：US17301780

申请日：2021-04-14

Applicant: NXP B.V.

Inventor： Jan-Peter Schat ,  Fabrice Poulard ,  Andreas Lentz

IPC: G06F21/00 ,  H04L9/08 ,  H04L9/32

Abstract: A method for securing an integrated circuit chip includes obtaining a first value from a first storage area in the chip, obtaining a second value from a second storage area in the chip, generating a third value based on the first value and the second value, and converting a first opcode command obfuscated as a second opcode command into a non-obfuscated form of the first opcode command based on the third value. The first value corresponds to a physically unclonable function (PUF) of the chip. The second value is a key including information indicating a type of obfuscation performed to obfuscate the first opcode command as the second opcode command. The third value may be an inversion flag indicating a type of obfuscation performed to obfuscate the first opcode command as the second opcode command.

公开(公告)号：US11449611B2

公开(公告)日：2022-09-20

申请号：US16417821

申请日：2019-05-21

Applicant: NXP B.V.

Inventor： Jan-Peter Schat

IPC: G06F21/56 ,  G06N20/00 ,  G06F21/71

Abstract: An apparatus includes integrated circuitry (IC) and a further circuit. The IC includes internal circuits having sensitive/secret data (SSD) to be maintained as confidential relative to a suspect Hardware Trojan (HT) and including access ports through which information associated with the internal circuits is accessible by external circuitry associated with the HT. The further circuit to learn behavior of the internal circuits that is unique to the integrated circuitry under different operating conditions involving the internal circuits, involving the SSD and involving other data that is functionally associated with an application of the integrated circuitry.

公开(公告)号：US11435940B2

公开(公告)日：2022-09-06

申请号：US17248661

申请日：2021-02-02

Applicant: NXP B.V.

Inventor： Jan-Peter Schat ,  Mohamed Azimane

IPC: G06F3/06 ,  G11C29/04 ,  G11C29/36 ,  G11C29/18

Abstract: An integrated circuit device includes an array of read/write memory cells, application logic circuitry, and address decoder circuitry coupled to receive input from the application logic circuitry and to provide output to the array of memory cells. The address decoder circuitry is reversible by having a bijective transfer function from the inputs to the outputs of the address decoder circuitry, and conservative by having the same number of 1's at the input and the output. During a test, the application logic circuitry provides a test value and test ancilla bits to the address decoder circuitry. During normal operation, the application logic circuitry provides an application memory address and constant ancilla bits to the address decoder circuitry.

公开(公告)号：US20220244881A1

公开(公告)日：2022-08-04

申请号：US17248661

申请日：2021-02-02

Applicant: NXP B.V.

Inventor： Jan-Peter Schat ,  Mohamed Azimane

IPC: G06F3/06

Abstract: An integrated circuit device includes an array of read/write memory cells, application logic circuitry, and address decoder circuitry coupled to receive input from the application logic circuitry and to provide output to the array of memory cells. The address decoder circuitry is reversible by having a bijective transfer function from the inputs to the outputs of the address decoder circuitry, and conservative by having the same number of 1's at the input and the output. During a test, the application logic circuitry provides a test value and test ancilla bits to the address decoder circuitry. During normal operation, the application logic circuitry provides an application memory address and constant ancilla bits to the address decoder circuitry.

公开(公告)号：US20220158644A1

公开(公告)日：2022-05-19

申请号：US17450190

申请日：2021-10-07

Applicant: NXP B.V.

Inventor： Jan-Peter Schat

IPC: H03L7/093 ,  H03L7/099

Abstract: The disclosure relates to detecting jitter in phase locked loop (PLL) circuits. Embodiments disclosed include a phase-locked loop, PLL (500) comprising: a phase comparison module (201); a loop filter (102); a voltage controller oscillator, VCO (103); a feedback divider (104); and a jitter evaluation module (502), the phase comparison module (201) comprising a phase comparator (202) and a measurement module (204) configured to detect a metastable output in the phase comparator (202) over active clock cycles of application and feedback clock signals (105, 106) input to the phase comparison module (201) and provide an output signal (208) to the jitter evaluation module (502) indicating a metastability resolution time for the phase comparator (202), the jitter evaluation module (210) being configured to provide an output indicative of jitter based on the metastability resolution time.

公开(公告)号：US11215694B2

公开(公告)日：2022-01-04

申请号：US16265141

申请日：2019-02-01

Applicant: NXP B.V.

Inventor： Jan-Peter Schat ,  Abdellatif Zanati

IPC: G01S7/40 ,  G01S7/35 ,  G01S13/34 ,  G01S13/931 ,  G01S7/03 ,  G01R31/28 ,  G06F11/27 ,  H04B17/14 ,  G01R31/3187 ,  H04B17/19

Abstract: A radar unit (100, 300) is described that comprises: a frequency generation circuit (103, 106, 303, 306) configured to generate a millimetre wave, mmW, frequency modulated continuous wave, FMCW, transmit signal comprising a plurality of chirps; a transmitter circuit (108, 102, 308, 302) configured to transmit the generated mmW FMCW transmit signal: a receiver circuit (104, 110, 304, 310) configured to receive an echo of the mmW FMCW transmit signal; and a built-in self-test, BIST, circuit (140, 340) coupled to the receiver circuit (104, 110, 304, 310) and configured to process the echo of the mmW FMCW transmit signal. The receiver circuit (104, 110, 304, 310) is configured to operate with at least two different paths for at least two successive chirps of the mmW FMCW transmit signal and create therefrom at least two respective received chirp signals; and the BIST circuit (140, 340) is configured to process and compare the at least two respective received chirp signals and determine therefrom an operational state of at least one circuit or component within the receiver circuit (104, 110, 304, 310).