公开(公告)号：US20230120079A1

公开(公告)日：2023-04-20

申请号：US17504046

申请日：2021-10-18

Applicant: NXP USA, Inc.

Inventor： Joseph Staudinger ,  Edward Provo Wallis Horne ,  Matthew Russell Greene ,  Johannes Lambertus Holt

IPC: H03F3/195 ,  H03F3/24 ,  H03F1/02 ,  H03F1/56

Abstract: an amplifier having an input terminal and an output terminal. The input terminal is configured to receive a radio frequency (RF) input signal. The device includes an output network coupled to the output terminal of the power amplifier and a first passively tunable integrated circuit (PTIC) coupled to the output network. The first PTIC includes a direct-current (DC) bias voltage input terminal configured to receive a fixed bias voltage, a control signal input terminal configured to receive a time-varying control signal, wherein the fixed bias voltage in combination with the time-varying control signal sets an operating reference point of the first PTIC, and an input terminal electrically connected to the output terminal of the amplifier, wherein a change in an output voltage signal generated by the power amplifier causes the first PTIC to modify a first effective impedance of a load presented to the power amplifier via the output network.

公开(公告)号：US20230115944A1

公开(公告)日：2023-04-13

申请号：US17497658

申请日：2021-10-08

Applicant: NXP USA, Inc.

Inventor： Venkata Naga Koushik Malladi ,  Joseph Staudinger

IPC: H03H7/01 ,  H01P5/22

Abstract: Embodiments of a method and an apparatus for a quadrature hybrid are disclosed. In an embodiment, a quadrature hybrid includes a first port, a second port, a third port, a fourth port, first, second, and third inductors, first, second, third, and fourth capacitors, and a first variable capacitor tuning network connected between the first port and the fourth port, and a second variable capacitor tuning network connected between the second port and the third port.

公开(公告)号：US10784862B1

公开(公告)日：2020-09-22

申请号：US16566710

申请日：2019-09-10

Applicant: NXP USA, Inc.

Inventor： Venkata Naga Koushik Malladi ,  Joseph Staudinger

IPC: H03K17/693 ,  H03F3/217 ,  H04B1/16 ,  H03F3/19 ,  H03F3/45 ,  H03K17/0416 ,  H03K17/16

Abstract: Embodiments described herein include radio frequency (RF) switches. In general, the embodiments described herein selectively bias the output terminals of one or more switching transistors in the RF switch. Such coupling can provide a bias that significantly reduces the effects of gate-lag. In one embodiment, the RF switch includes an antenna node, a first input/output (I/O) node, a second I/O node, a field-effect transistor (FET), a FET stack, and a bias coupling circuit. In this embodiment the bias coupling circuit electrically couples a gate terminal of the FET to one or more FET output terminals of the FET stack to provide a bias voltage to the output terminal(s).

公开(公告)号：US20190319587A1

公开(公告)日：2019-10-17

申请号：US15952889

申请日：2018-04-13

Applicant: NXP USA, Inc.

Inventor： Ramanujam Srinidhi Embar ,  Tushar Sharma ,  Joseph Staudinger

IPC: H03F1/02 ,  H03F3/195 ,  H03F3/213 ,  H03F1/56 ,  H05K1/18 ,  H05K1/02 ,  H01L23/498 ,  H01L23/66 ,  H01L23/00

Abstract: Hybrid power amplifier circuits, modules, or systems, and methods of operating same, are disclosed herein. In one example embodiment, a hybrid power amplifier circuit includes a preliminary stage amplification device, a final stage amplification device, and intermediate circuitry at least indirectly coupling the preliminary stage amplification device and the final stage amplification device. The intermediate circuitry includes a low-pass circuit and a high-pass circuit, and the hybrid power amplifier circuit is configured to amplify a first signal component at a fundamental frequency. Due at least in part to the intermediate circuitry, a phase of a second signal component at a harmonic frequency that is a multiple of the fundamental frequency is shifted.

公开(公告)号：US10432148B2

公开(公告)日：2019-10-01

申请号：US16274016

申请日：2019-02-12

Applicant: NXP USA, Inc.

Inventor： Abdulrhman M. S. Ahmed ,  Mario M. Bokatius ,  Paul R. Hart ,  Joseph Staudinger ,  Richard E. Sweeney

IPC: H03F1/02 ,  H03F3/21 ,  H03F3/60 ,  H03F3/68 ,  H03F3/189 ,  G06G7/10 ,  H03G1/00 ,  H04L27/22 ,  G06F13/42 ,  H03F3/19 ,  H04L7/00

Abstract: Embodiments of circuits for use with an amplifier that includes multiple amplifier paths include a first circuit and a second circuit in parallel with the first circuit. The first circuit includes a first input coupled to a first power divider output, a first output coupled to a first amplifier path of the multiple amplifier paths, and a first adjustable phase shifter and a first attenuator series coupled between the first input and the first output. The second circuit includes a second input coupled to a second power divider output, a second output coupled to a second amplifier path of the multiple amplifier paths, and a second adjustable phase shifter coupled between the second input and the second output.

公开(公告)号：US10148228B2

公开(公告)日：2018-12-04

申请号：US15384601

申请日：2016-12-20

Applicant: NXP USA, Inc.

Inventor： Donald Vernon Hayes ,  Joseph Staudinger ,  Abdulrhman M. S. Ahmed

IPC: H03F1/02 ,  H03F3/195 ,  H03F3/24 ,  H03F3/68

Abstract: A Doherty amplifier is able to enhance efficiency in low-power and high-power RF communication states by enabling carrier and peaking amplifiers as required, and controlling bias modulation, depending on traffic loading levels in each of a set of consecutive communications timeslots. For example, if, in a low-power state, traffic loading levels do not exceed a relatively lower threshold in a communications timeslot, carrier amplifiers are selectively enabled as needed, peaking amplifiers are not enabled, and carrier amplifier bias levels are kept substantially constant. If, in an intermediate-power state, the lower threshold is exceeded but a relatively higher threshold is not exceeded, all carrier amplifiers are enabled, peaking amplifiers are selectively enabled, and bias levels are kept substantially constant. If, in a high-power state, the higher threshold is exceeded, all carrier and peaking amplifiers can be enabled, and the peaking amplifier bias tracks the RF envelope of the received RF signal.

公开(公告)号：US10033374B2

公开(公告)日：2018-07-24

申请号：US15601567

申请日：2017-05-22

Applicant: NXP USA, Inc.

Inventor： Bruce M. Green ,  Enver Krvavac ,  Joseph Staudinger

IPC: H03K17/16 ,  G06F1/32

Abstract: An embodiment of a device includes a terminal, an active transistor die electrically coupled to the terminal, a detector configured to sense a signal characteristic on the terminal, and control circuitry electrically coupled to the active transistor die and to the detector, wherein the active transistor die, detector, and control circuitry are coupled to a package. The control circuitry may include a control element and a control device. Based on the signal characteristic, the control circuitry controls which of multiple operating states the device operates. A method for controlling the operating state of the device includes sensing, using the detector, a signal characteristic at the terminal, and determining, using the control device, whether the signal characteristic conforms to a pre-set criteria, and when the signal characteristic does not conform to the pre-set criteria, modifying the state of the control element to alter the operating state of the device.

公开(公告)号：US20250055171A1

公开(公告)日：2025-02-13

申请号：US18366965

申请日：2023-08-08

Applicant: NXP USA, Inc.

Inventor： Joseph Staudinger ,  Michael Lee Fraser

IPC: H01P5/16 ,  H03F3/20

Abstract: A quadrature coupler includes four ports, four inductors, and six capacitors. The first through third capacitors are coupled in series between the first and fourth ports. A first intermediate node is between the first and second capacitors. A second intermediate node is between the second and third capacitors. The fourth through sixth capacitors are coupled in series between the second and third ports. A third intermediate node is between the fourth and fifth capacitors, and a fourth intermediate node is between the fifth and sixth capacitors. The first inductor is coupled between the first and second ports. The second inductor is coupled between the first and third intermediate nodes. The third inductor is coupled between the second and fourth intermediate nodes. The fourth inductor is coupled between the fourth and third ports. Variable tuning networks may be coupled between the first and fourth ports and the second and third ports.

公开(公告)号：US11757422B2

公开(公告)日：2023-09-12

申请号：US17497658

申请日：2021-10-08

Applicant: NXP USA, Inc.

Inventor： Venkata Naga Koushik Malladi ,  Joseph Staudinger

IPC: H03H7/01 ,  H01P5/22

CPC classification number: H03H7/0115 ,  H01P5/227

Abstract: Embodiments of a method and an apparatus for a quadrature hybrid are disclosed. In an embodiment, a quadrature hybrid includes a first port, a second port, a third port, a fourth port, first, second, and third inductors, first, second, third, and fourth capacitors, and a first variable capacitor tuning network connected between the first port and the fourth port, and a second variable capacitor tuning network connected between the second port and the third port.

公开(公告)号：US20220158590A1

公开(公告)日：2022-05-19

申请号：US16951781

申请日：2020-11-18

Applicant: NXP USA, Inc.

Inventor： Joseph Staudinger ,  Matthew Russell Greene ,  Edward Provo Wallis Horne ,  Johannes Lambertus Holt ,  Peter Zahariev Rashev

IPC: H03F1/02 ,  H03F3/195 ,  H03F3/24 ,  H03F1/56 ,  H03F3/60

Abstract: Aspects of the subject disclosure may include a Doherty amplifier that includes a carrier amplifier having an output terminal, an output network coupled to the output terminal, and a peaking amplifier, wherein the output network comprises a non-linear reactance component, and wherein the non-linear reactance component changes an effective impedance of a load presented to the carrier amplifier when the peaking amplifier is off. Other embodiments are disclosed.