公开(公告)号：US20070033380A1

公开(公告)日：2007-02-08

申请号：US11493865

申请日：2006-07-25

Applicant: Mathieu Lisart ,  Nicolas Demange

Inventor： Mathieu Lisart ,  Nicolas Demange

IPC: G06F15/00

CPC classification number: G06F21/556 ,  G11C7/06 ,  G11C7/1006 ,  G11C7/24

Abstract: A method processes parallel electrical signals, using parallel processing circuits that process successive cycles of electrical signals according to a rule for allocating electrical signals to the processing circuits. The method comprises, between the processing cycles, a step of modifying the rule for allocating electrical signals to the processing circuits, so that a processing circuit processes electrical signals of different ranks during different processing cycles. The method can be applied particularly to secure a memory during read phases of the memory and of an integrated circuit with a microprocessor using such a memory.

Abstract translation: 一种方法使用根据用于将电信号分配给处理电路的规则处理电信号的连续循环的并行处理电路来处理并行电信号。 该方法包括在处理周期之间，修改用于将电信号分配给处理电路的规则的步骤，使得处理电路在不同处理周期期间处理不同等级的电信号。 该方法可以特别用于在存储器的读取阶段和使用这种存储器的微处理器的集成电路中保护存储器。

公开(公告)号：US06909626B2

公开(公告)日：2005-06-21

申请号：US10402853

申请日：2003-03-28

Applicant: Salvatore Torrisi ,  Giampiero Sberno ,  Nicolas Demange

Inventor： Salvatore Torrisi ,  Giampiero Sberno ,  Nicolas Demange

IPC: G11C11/22

CPC classification number: G11C11/22

Abstract: A method and circuit for accessing a memory location comprising at least one respective ferroelectric storage unit of a matrix of ferroelectric storage units, the memory location is selected by connecting a first terminal of a ferroelectric storage element of the at least one respective storage unit to a respective access line to the memory location; at least another memory location to which is not intended to be accessed is also selected. A second terminal of the ferroelectric storage element is biased to a prescribed access electric potential, and an electric potential on the access line is sensed; the second terminal of the ferroelectric storage elements of the other memory location is also biased to the access potential.

Abstract translation: 一种用于访问包括铁电存储单元矩阵的至少一个相应铁电存储单元的存储器位置的方法和电路，通过将至少一个相应存储单元的铁电存储元件的第一端子连接到 相应的访问线路到内存位置; 还选择至少另一个不想访问的存储器位置。 铁电存储元件的第二端子被偏置到规定的访问电位，并且感测访问线路上的电位; 另一个存储器位置的铁电存储元件的第二端子也被偏置到存取电位。

公开(公告)号：US06795330B2

公开(公告)日：2004-09-21

申请号：US10226642

申请日：2002-08-23

Applicant: Nicolas Demange ,  Salvatore Torrisi ,  Giampiero Sberno

Inventor： Nicolas Demange ,  Salvatore Torrisi ,  Giampiero Sberno

IPC: G11C1122

CPC classification number: G11C11/22

Abstract: A method of reading and restoring data stored in a ferroelectric memory cell is disclosed. The cell includes a first transistor and first ferroelectric capacitor connected, in series with each other, between a first bitline and an auxiliary line, a second transistor and second ferroelectric capacitor connected, in series with each other, between a second bitline and the auxiliary line, the first and second transistors having respective control terminals connected to a common wordline. The reading method includes precharging the first and second capacitors, applying a read pulse to the cell such that the state of the first capacitor is changed, reading the cell by a sensing means, and restoring the first capacitor to an initial state. Advantageously, the reading method further includes changing the state of the second capacitor during the step of restoring the first capacitor, and further restoring the second capacitor to an initial state, such that the voltages being applied to the transistors during any of the steps are lower than a voltage reference of the cell. Also disclosed is a method of writing and restoring data stored in a ferroelectric memory cell.

Abstract translation: 公开了一种读取和恢复存储在铁电存储单元中的数据的方法。 该单电池包括：第一位线和辅助线之间串联连接的第一晶体管和第一铁电电容器，第一晶体管和第二铁电电容器彼此串联连接在第二位线和辅助线之间， ，第一和第二晶体管具有连接到公共字线的各个控制端子。 读取方法包括对第一和第二电容器进行预充电，向单元施加读取脉冲，使得第一电容器的状态改变，通过感测装置读取单元，并将第一电容器恢复到初始状态。 有利地，读取方法还包括在恢复第一电容器的步骤期间改变第二电容器的状态，并且还将第二电容器恢复到初始状态，使得在任何步骤期间施加到晶体管的电压较低 比电池的电压基准。 还公开了一种写入和恢复存储在铁电存储单元中的数据的方法。

公开(公告)号：US06466059B1

公开(公告)日：2002-10-15

申请号：US09249834

申请日：1999-02-12

Applicant: Maurizio Gaibotti ,  Nicolas Demange

Inventor： Maurizio Gaibotti ,  Nicolas Demange

IPC: G01R1900

CPC classification number: G11C16/24 ,  G11C7/062 ,  G11C7/12 ,  G11C16/28

Abstract: A sense amplifier of the type coupled to a reference bit line and at least one cell array bit line. The sense amplifier includes an amplifying stage and a current voltage conversion circuit that compare a reference current from the reference bit line and a cell current from the cell array bit line. The current-voltage conversion circuit includes a voltage setting circuit for setting predetermined voltages on the reference bit line and the cell array bit line, a load circuit for the reference bit line and the cell array bit line, and current mirror circuits for mirroring the reference current and the cell current into the amplifying stage. The load circuit for the reference bit line and the current mirror circuit for the reference current are different circuits, and the load circuit for the reference bit line includes a transistor that mirrors a predetermined current that is generated outside of the sense amplifier. Another embodiment provides a sense amplifier that includes a first current mirror having one branch coupled to a cell array bit line, and a second current mirror having a branch coupled to both a reference bit line and another branch of the first current mirror. In one preferred embodiment, the second current mirror mirrors a predetermined current that is generated outside of the sense amplifier. A method for sensing the current of a memory cell in a memory device is also provided.

Abstract translation: 一种耦合到参考位线和至少一个单元阵列位线的读出放大器。 读出放大器包括放大级和电流电压转换电路，其比较来自参考位线的参考电流和来自单元阵列位线的单元电流。 电流 - 电压转换电路包括用于设置参考位线和单元阵列位线上的预定电压的电压设置电路，用于参考位线和单元阵列位线的负载电路以及用于镜像参考电流的电流镜电路 电流和电池电流进入放大级。 用于参考位线的负载电路和用于参考电流的电流镜电路是不同的电路，并且用于参考位线的负载电路包括反映在读出放大器外部产生的预定电流的晶体管。 另一实施例提供了一种读出放大器，其包括具有耦合到单元阵列位线的一个分支的第一电流镜和具有耦合到第一电流镜的另一分支的分支的第二电流镜。 在一个优选实施例中，第二电流镜反映在读出放大器外部产生的预定电流。 还提供了用于感测存储器件中的存储单元的电流的方法。

公开(公告)号：US5841314A

公开(公告)日：1998-11-24

申请号：US663524

申请日：1996-06-13

Applicant: Alessandro Brigati ,  Nicolas Demange ,  Maxence Aulas ,  Marc Guedj

Inventor： Alessandro Brigati ,  Nicolas Demange ,  Maxence Aulas ,  Marc Guedj

IPC: G11C11/407 ,  G05F3/20 ,  G11C16/06 ,  G11C17/00 ,  H02M3/07 ,  H03K3/01 ,  G11C7/00

CPC classification number: H02M3/073 ,  G05F3/205

Abstract: Disclosed is a charge pump type of negative voltage generator circuit, constructed on a P type substrate and supplying a negative voltage at one output by the pumping of negative charges in n series-connected pumping cells, n being an integer, these pumping cells including P type transistors whose wells are connected to a node to be positively biased. This circuit includes a switching circuit for selectively supplying, at the node, a voltage for biasing of the wells that is greater than or equal to the potential present at the output so long as this potential is greater than a positive reference voltage, and provides a voltage of fixed value for biasing of the wells when the potential present at the output is smaller than the reference voltage. Thus, the appearance of latchup phenomena in the transistors of the pumping cells is prevented.

Abstract translation: 公开了一种电荷泵型负电压发生器电路，其构造在P型基板上，并通过在n个串联的泵浦单元中泵送负电荷而在一个输出端提供负电压，n为整数，这些泵浦单元包括P 其阱连接到节点以进行正偏置。 该电路包括切换电路，用于在节点处选择性地提供用于偏置井的电压，只要该电位大于正参考电压，该电压大于或等于存在于输出处的电位，并且提供 当输出端存在的电位小于参考电压时，用于偏置阱的固定值的电压。 因此，防止泵送单元的晶体管中的闭锁现象的出现。