公开(公告)号：US5652720A

公开(公告)日：1997-07-29

申请号：US573897

申请日：1995-12-18

Applicant: Maxence Aulas ,  Alessandro Brigati ,  Nicolas Demange ,  Marc Guedj

Inventor： Maxence Aulas ,  Alessandro Brigati ,  Nicolas Demange ,  Marc Guedj

IPC: G11C17/00 ,  G11C16/02 ,  G11C16/34 ,  G11C11/34

CPC classification number: G11C16/3431 ,  G11C16/3418

Abstract: The present invention concerns an electrically programmable memory and a method for writing within this memory. In order to avoid the degradation of information in a memory cell following a number of write cycles in the other cells of the same row, the present invention includes a sequence to be carried out before each write cycle of a word within a row. A systematic reading of all the words of a row by using three different read reference potentials is performed in order to find a cell that gives non-compatibility results between any two of the three read cycles. The words of the row are stored in a register. If a non-compatible result is found, which indicates a degradation of information in the row, a systematic re-write of all the words of the row is carried out.

Abstract translation: 本发明涉及一种电可编程存储器和一种用于在该存储器内写入的方法。 为了避免在同一行的其他单元中的多个写周期之后的存储单元中的信息的劣化，本发明包括在行内的单词的每个写入周期之前要执行的序列。 执行通过使用三个不同的读取参考电位对一行中的所有单词的系统读取，以便找到在三个读取周期中的任何两个之间给出不兼容结果的单元。 行中的单词存储在一个寄存器中。 如果发现不兼容的结果，表示该行中信息的恶化，则执行该行中所有字的系统重新写入。

公开(公告)号：US06356987B1

公开(公告)日：2002-03-12

申请号：US09266045

申请日：1999-03-10

Applicant: Maxence Aulas

Inventor： Maxence Aulas

IPC: G06F1300

CPC classification number: G06F13/4243

Abstract: The present invention deals with the control of a data bus by a microcontroller, taking into account the fact that memory output drivers require a finite amount of time to electrically release the bus after an output operation. Each memory has an associated wait state number for selectively placing the microcontroller in a wait state of variable length subsequent to a read operation and prior to the next I/O operation.

Abstract translation: 本发明考虑到存储器输出驱动器在输出操作之后需要有限的时间来电释放总线的事实，涉及微控制器对数据总线的控制。 每个存储器具有相关联的等待状态号，用于在读取操作之后和在下一个I / O操作之前选择性地将微控制器置于可变长度的等待状态。

公开(公告)号：US5841314A

公开(公告)日：1998-11-24

申请号：US663524

申请日：1996-06-13

Applicant: Alessandro Brigati ,  Nicolas Demange ,  Maxence Aulas ,  Marc Guedj

Inventor： Alessandro Brigati ,  Nicolas Demange ,  Maxence Aulas ,  Marc Guedj

IPC: G11C11/407 ,  G05F3/20 ,  G11C16/06 ,  G11C17/00 ,  H02M3/07 ,  H03K3/01 ,  G11C7/00

CPC classification number: H02M3/073 ,  G05F3/205

Abstract: Disclosed is a charge pump type of negative voltage generator circuit, constructed on a P type substrate and supplying a negative voltage at one output by the pumping of negative charges in n series-connected pumping cells, n being an integer, these pumping cells including P type transistors whose wells are connected to a node to be positively biased. This circuit includes a switching circuit for selectively supplying, at the node, a voltage for biasing of the wells that is greater than or equal to the potential present at the output so long as this potential is greater than a positive reference voltage, and provides a voltage of fixed value for biasing of the wells when the potential present at the output is smaller than the reference voltage. Thus, the appearance of latchup phenomena in the transistors of the pumping cells is prevented.

Abstract translation: 公开了一种电荷泵型负电压发生器电路，其构造在P型基板上，并通过在n个串联的泵浦单元中泵送负电荷而在一个输出端提供负电压，n为整数，这些泵浦单元包括P 其阱连接到节点以进行正偏置。 该电路包括切换电路，用于在节点处选择性地提供用于偏置井的电压，只要该电位大于正参考电压，该电压大于或等于存在于输出处的电位，并且提供 当输出端存在的电位小于参考电压时，用于偏置阱的固定值的电压。 因此，防止泵送单元的晶体管中的闭锁现象的出现。

公开(公告)号：US6011717A

公开(公告)日：2000-01-04

申请号：US666849

申请日：1996-06-19

Applicant: Alessandro Brigati ,  Nicolas Demange ,  Maxence Aulas ,  Marc Guedj

Inventor： Alessandro Brigati ,  Nicolas Demange ,  Maxence Aulas ,  Marc Guedj

IPC: G11C17/00 ,  G11C16/04 ,  G11C16/14 ,  G11C16/00

CPC classification number: G11C16/0433 ,  G11C16/14

Abstract: An EEPROM is organized in matrix form in word lines and bit lines. Storage cells are placed at the intersections of these lines. The cells include floating gate storage transistors. Groups of cells having separate bit lines but sharing a word line are created. Each group is connected to a group selection transistor. The group selection transistor selectively connects the control gates of the storage transistors to control lines, which provide potentials for enabling programming, erasure or reading of the storage transistors.

Abstract translation: 在字线和位线中以矩阵形式组织EEPROM。 存储单元被放置在这些线的交点处。 这些单元包括浮栅存储晶体管。 创建具有分开的位线但共享字线的单元组。 每组连接到组选择晶体管。 组选择晶体管选择性地将存储晶体管的控制栅极连接到控制线，控制线提供用于实现存储晶体管的编程，擦除或读取的电位。

公开(公告)号：US5796297A

公开(公告)日：1998-08-18

申请号：US666733

申请日：1996-06-17

Applicant: Alessandro Brigati ,  Nicolas Demange ,  Maxence Aulas ,  Marc Guedj

Inventor： Alessandro Brigati ,  Nicolas Demange ,  Maxence Aulas ,  Marc Guedj

IPC: G11C17/00 ,  G11C16/06 ,  H03K17/693 ,  H03K19/00

CPC classification number: H03K17/693 ,  Y10T307/696 ,  Y10T307/832 ,  Y10T307/858

Abstract: A selector switch circuit comprises an input terminal to receive a positive voltage, an input terminal to receive a negative voltage, a command input terminal to receive a first command logic signal and an output terminal to provide an output voltage. The output is connected selectively to one of the input terminals, the first and second input terminals being connected to the output terminal by means of a first transistor and a second transistor and the circuit comprising control means for the production, as a function of the command signal, of the control voltages applied to the control gates of the transistors for the selective connection of the output terminal to one of the input terminals.

Abstract translation: 选择器开关电路包括用于接收正电压的输入端子，用于接收负电压的输入端子，用于接收第一命令逻辑信号的命令输入端子和输出端子以提供输出电压。 输出被选择性地连接到一个输入端，第一和第二输入端通过第一晶体管和第二晶体管连接到输出端，并且该电路包括作为指令的函数的用于产生的控制装置 施加到晶体管的控制栅极的控制电压的信号，用于选择性地将输出端子连接到输入端子之一。

公开(公告)号：US5760638A

公开(公告)日：1998-06-02

申请号：US664083

申请日：1996-06-13

Applicant: Alessandro Brigati ,  Nicolas Demange ,  Maxence Aulas ,  Marc Guedj

Inventor： Alessandro Brigati ,  Nicolas Demange ,  Maxence Aulas ,  Marc Guedj

IPC: G11C17/00 ,  G11C16/06 ,  H02M3/07 ,  H03K3/02 ,  H03K3/06

CPC classification number: H02M3/073

Abstract: A phase generator circuit cyclically produces a first pair of phase signals and a second pair of phase signals, comprising a first circuit to produce a first phase of each pair of phase signals, these first phase signals being non-overlapping and switching over between a voltage 0 and a voltage VCC, and second and third circuits for the production, from the first phase signals, respectively of the second phase of the first pair and the second phase of the second pair of phase signals, these second phase signals being non-overlapping with the first phase signals and switching over between a negative voltage -V and a voltage VCC. The disclosure finds application in the piloting of charge pump type of negative voltage generator circuit.

Abstract translation: 相位发生器电路循环地产生第一对相位信号和第二对相位信号，包括第一电路以产生每对相位信号的第一相位，这些第一相位信号是不重叠的，并且在电压 0和电压VCC，以及用于产生的第二和第三电路，分别来自第一对的第二相和第二对相位信号的第二相的第一相位信号，这些第二相位信号是不重叠的 第一相信号并在负电压-V和电压VCC之间切换。 本发明适用于负荷电压型负压发电机电路的试点。