公开(公告)号：US20120127239A1

公开(公告)日：2012-05-24

申请号：US13300386

申请日：2011-11-18

Applicant: Hisanori Maruyama ,  Noboru Asauchi

Inventor： Hisanori Maruyama ,  Noboru Asauchi

IPC: B41J2/14

CPC classification number: B41J2/1753 ,  B41J2/1752 ,  B41J2/17523 ,  B41J2/17546 ,  B41J2/17553 ,  B41J29/13

Abstract: A circuit substrate includes a first terminal connected to a storage device, a second terminal to which voltage higher than voltage which is applied to the first terminal is applied, and a third terminal. The third terminal is disposed adjacent to the first terminal and the second terminal and connected to an overvoltage detection section provided in a printer. A convex portion is provided on a substrate surface between the first terminal and the second terminal, and a configuration is made such that a liquid droplet easily spreads from the second terminal to the third terminal rather than the liquid droplet spreading from the second terminal to the first terminal.

Abstract translation: 电路基板包括连接到存储装置的第一端子，施加到施加到第一端子的电压高于的电压的第二端子和第三端子。 第三端子与第一端子和第二端子相邻设置并连接到设置在打印机中的过电压检测部分。 在第一端子和第二端子之间的衬底表面上设置凸部，并且使得液滴容易从第二端子扩散到第三端子，而不是液滴从第二端子扩展到第二端子 第一个终端。

公开(公告)号：US20120047410A1

公开(公告)日：2012-02-23

申请号：US13215130

申请日：2011-08-22

Applicant: Jun Sato ,  Shuichi Nakano ,  Noboru Asauchi

Inventor： Jun Sato ,  Shuichi Nakano ,  Noboru Asauchi

IPC: G06F12/00 ,  G06F11/22 ,  G11C29/52

CPC classification number: G06F3/1203 ,  B41J2/1753 ,  B41J2/17546 ,  G06F3/121 ,  G06F3/1229 ,  G06F3/1234 ,  G06K15/4075

Abstract: A storage device according to some aspects of the invention includes a communication unit configured to perform processing for communication with a host apparatus; a storage unit configured to have a first memory area and a second memory area that store therein received data from the host apparatus, and memory area selection information; a memory control unit configured to select one of the first memory area and the second memory area as a memory area for reading, select the other one thereof as a memory area for writing, and perform control of reading and writing; and an increment determination unit configured to compare a value of data having been read out from the memory area for reading by the memory control unit and a value of the received data to determine a magnitude relation therebetween.

Abstract translation: 根据本发明的一些方面的存储装置包括：通信单元，被配置为执行与主机设备通信的处理; 存储单元，被配置为具有存储来自所述主机装置的接收数据的第一存储区域和第二存储区域以及存储区域选择信息; 存储器控制单元，被配置为选择第一存储区域和第二存储器区域中的一个作为用于读取的存储区域，选择其中的另一个作为用于写入的存储区域，并执行读取和写入的控制; 以及增量确定单元，被配置为将从存储器区域读出的数据的值与存储器控制单元的读取值和所接收的数据的值进行比较，以确定其间的幅度关系。

公开(公告)号：US20110292102A1

公开(公告)日：2011-12-01

申请号：US13113859

申请日：2011-05-23

Applicant: Noboru Asauchi

Inventor： Noboru Asauchi

IPC: B41J29/38 ,  G11C7/00

CPC classification number: B41J2/17546

Abstract: A storage device electrically connected to a host circuit includes a data receiving unit, determination unit, and a data transmitting unit. The data receiving unit receives data including first data which are to be written in a memory array and second data which are generated based on the first data from the host circuit. The determination unit determines consistency between the first data and the second data. The data transmitting unit transmits a result of the determination to the host circuit.

Abstract translation: 电连接到主机电路的存储装置包括数据接收单元，确定单元和数据发送单元。 数据接收单元接收包括要写入存储器阵列的第一数据和基于来自主机电路的第一数据产生的第二数据的数据。 确定单元确定第一数据和第二数据之间的一致性。 数据发送单元将确定结果发送给主机电路。

公开(公告)号：US20110087853A1

公开(公告)日：2011-04-14

申请号：US12892093

申请日：2010-09-28

Applicant: Shinichi Yamada ,  Yasuhiko Kosugi ,  Noboru Asauchi ,  Yoshihiro Nakamura

Inventor： Shinichi Yamada ,  Yasuhiko Kosugi ,  Noboru Asauchi ,  Yoshihiro Nakamura

IPC: G06F1/08 ,  G06F12/00 ,  G06F1/04

CPC classification number: G11C7/24

Abstract: A storage device includes a nonvolatile storage section; and a control section that controls the nonvolatile storage section, wherein the control section includes an access control section that outputs a clock for access control for performing access control of a read/write of the nonvolatile storage section, and performs access control of the read/write to the nonvolatile storage section, and a masking process section that performs the masking process of a reset signal on the basis of the clock for access control from the access control section, and supplies the reset signal after the masking process to the access control section.

Abstract translation: 存储装置包括：非易失性存储部; 以及控制部，其控制所述非易失性存储部，其中，所述控制部包括访问控制部，所述访问控制部输出用于进行所述非易失性存储部的读取/写入的访问控制的访问控制的时钟，并且执行所述读取​​/ 写入非易失性存储部分，以及屏蔽处理部分，其基于来自访问控制部分的访问控制的时钟执行复位信号的掩蔽处理，并且将掩蔽处理之后的复位信号提供给访问控制部分 。

公开(公告)号：US07499372B2

公开(公告)日：2009-03-03

申请号：US11420603

申请日：2006-05-26

Applicant: Noboru Asauchi ,  Eitaro Otsuka

Inventor： Noboru Asauchi ,  Eitaro Otsuka

IPC: G11C8/00

CPC classification number: G11C16/10 ,  G11C16/3454 ,  G11C2216/14

Abstract: When writing 16-bit write data to the memory array 100 which can store data of 8 bits per 1 row, the semiconductor memory device 10 first writes the upper 8 bits to the 1st write restricted row of the memory array 100. The increment controller 150 determines whether or not the value of the existing data written to the memory array 100 and the write data used for writing latched to the 8-bit latch register 170 match. When the existing data and the write data match, the increment controller 150 outputs the write enable signal WEN1 to the write/read controller 140 and executes the writing of the lower 8 bits of write data to the memory array 100.

Abstract translation: 当向可存储每1行8位数据的存储器阵列100写入16位写入数据时，半导体存储器件10首先将高8位写入存储器阵列100的第1写入限制行。增量控制器150 确定写入存储器阵列100的现有数据的值和用于写入到8位锁存寄存器170的写入数据是否匹配。 当现有数据和写入数据匹配时，增量控制器150将写入使能信号WEN1输出到写入/读取控制器140，并将写入数据的低8位写入存储器阵列100。

公开(公告)号：US07433260B2

公开(公告)日：2008-10-07

申请号：US11516941

申请日：2006-09-06

Applicant: Noboru Asauchi

Inventor： Noboru Asauchi

IPC: G11C8/00

CPC classification number: G06F12/1433 ,  G11C7/24

Abstract: The operation code decoder 204 having received an access enable signal EN acquires and decodes the command, and sends the decoded command to the read/write controller 206. In the event that the received command is a write command, the read/write controller 206 acquires access control information from the fourth address following the head address of the memory array 201. In the event that the acquired access control information indicates that write operations are prohibited, the read/write controller 206 does not send the write command received from the operation code decoder 204 to the I/O controller 205.

Abstract translation: 已经接收到访问使能信号EN的操作码解码器204获取并解码该命令，并且将解码的命令发送到读/写控制器206。 在接收到的命令是写命令的情况下，读/写控制器206从存储器阵列201的头地址之后的第四地址获取访问控制信息。 在获取的访问控制信息指示禁止写入操作的情况下，读/写控制器206不将从操作码解码器204接收到的写命令发送到I / O控制器205。

公开(公告)号：US20080212379A1

公开(公告)日：2008-09-04

申请号：US11420603

申请日：2006-05-26

Applicant: Noboru Asauchi ,  Eitaro Otsuka

Inventor： Noboru Asauchi ,  Eitaro Otsuka

IPC: G11C7/00

CPC classification number: G11C16/10 ,  G11C16/3454 ,  G11C2216/14

Abstract: When writing 16-bit write data to the memory array 100 which can store data of 8 bits per 1 row, the semiconductor memory device 10 first writes the upper 8 bits to the 1st write restricted row of the memory array 100. The increment controller 150 determines whether or not the value of the existing data written to the memory array 100 and the write data used for writing latched to the 8-bit latch register 170 match. When the existing data and the write data match, the increment controller 150 outputs the write enable signal WEN1 to the write/read controller 140 and executes the writing of the lower 8 bits of write data to the memory array 100.

Abstract translation: 当将16位写数据写入可存储每1行8位数据的存储器阵列100时，半导体存储器件10首先将高8位写入存储器阵列100的第一写限制行。 增量控制器150确定写入存储器阵列100的现有数据的值和用于写入到8位锁存寄存器170的写入数据是否匹配。 当现有数据和写入数据匹配时，增量控制器150将写入使能信号WEN 1输出到写/读控制器140，并且执行写入数据的低8位的写入到存储器阵列100。

公开(公告)号：US07232209B2

公开(公告)日：2007-06-19

申请号：US10816167

申请日：2004-04-02

Applicant: Noboru Asauchi

Inventor： Noboru Asauchi

IPC: B41J2/175 ,  G08B13/14 ,  G03G15/00

CPC classification number: B41J2/17546

Abstract: An expendable container of the present invention includes a memory circuit. The memory circuit has a memory, an antenna being capable of establishing non-contact communication with an external receiver transmitter, and a controller controlling the non-contact communication and an access to the memory. The memory circuit has a plurality of modes including ID information confirmation mode and low power consumption mode. The memory circuit is capable of shifting to the low power consumption mode in response to a completion of confirmation of the ID information of the expendable container.

Abstract translation: 本发明的消耗性容器包括存储器电路。 存储器电路具有存储器，能够与外部接收器发送器建立非接触通信的天线以及控制非接触通信和对存储器的访问的控制器。 存储电路具有ID信息确认模式和低功耗模式的多种模式。 响应于完成对消耗性容器的ID信息的确认，存储电路能够转换到低功耗模式。

公开(公告)号：US20070030508A1

公开(公告)日：2007-02-08

申请号：US11542113

申请日：2006-10-04

Applicant: Noboru Asauchi

Inventor： Noboru Asauchi

IPC: G06K15/00

CPC classification number: B41J2/17546 ,  B41J13/103 ,  B41J29/393 ,  B41J2202/17 ,  G06K15/00

Abstract: The present invention provides a storage device that enables identification data to be readily rewritten and ensures normal completion of a data writing operation in a short time period. In the storage device of the invention, an ID comparator determines whether or not identification data transmitted from a host computer coincides with identification data stored in a memory array. In the case of coincidence, the ID comparator sends an access enable signal EN to an operation code decoder. The operation code decoder analyzes a write/read command, switches over a direction of data transfer with regard to the memory array based on a result of the analysis, and requires an I/O controller to change a high impedance setting of a signal line connecting with a data terminal DT. This series of processing allows access to an address in the memory array specified by a count on an address counter.

Abstract translation: 本发明提供一种能够容易地重写识别数据并确保在短时间内正常完成数据写入操作的存储装置。 在本发明的存储装置中，ID比较器确定从主计算机发送的识别数据是否与存储在存储器阵列中的识别数据一致。 在符合的情况下，ID比较器向操作码解码器发送访问使能信号EN。 操作码解码器分析写入/读取命令，基于分析结果切换关于存储器阵列的数据传输方向，并且需要I / O控制器来改变连接的信号线的高阻抗设置 与数据终端DT。 该系列处理允许访问由地址计数器上的计数指定的存储器阵列中的地址。

公开(公告)号：US20070019497A1

公开(公告)日：2007-01-25

申请号：US11458820

申请日：2006-07-20

Applicant: Noboru Asauchi

Inventor： Noboru Asauchi

IPC: G11C8/00

CPC classification number: G11C8/04 ,  G11C16/08

Abstract: In a semiconductor memory device 10, the maximum counter value in a carry-up unit 111 of an address counter 110 is set to 128 bits when an access request is for writing data to a memory array 100. On the other hand, in the semiconductor memory device 10, if the access request is for reading data from the memory array 100, the maximum counter value in the carry-up unit 111 of the address counter 110 is set to 256 bits. The result is that it is possible to reduce the circuit structure required for specifying the desired address in an EEPROM array 101 and a masked ROM array 102.

Abstract translation: 在半导体存储器件10中，当访问请求用于将数据写入存储器阵列100时，地址计数器110的进位单元111中的最大计数器值被设置为128位。 另一方面，在半导体存储器件10中，如果访问请求用于从存储器阵列100读取数据，则将地址计数器110的进位单元111中的最大计数器值设置为256位。 结果是可以减少在EEPROM阵列101和掩蔽的ROM阵列102中指定所需地址所需的电路结构。