公开(公告)号：US20100102857A1

公开(公告)日：2010-04-29

申请号：US12654323

申请日：2009-12-17

申请人： Takaaki Aoki ,  Shoji Mizuno ,  Shigeki Takahashi ,  Takashi Nakano ,  Nozomu Akagi ,  Yoshiyuki Hattori ,  Makoto Kuwahara ,  Kyoko Okada

发明人： Takaaki Aoki ,  Shoji Mizuno ,  Shigeki Takahashi ,  Takashi Nakano ,  Nozomu Akagi ,  Yoshiyuki Hattori ,  Makoto Kuwahara ,  Kyoko Okada

IPC分类号： H03K3/00 ,  H03K17/56

CPC分类号： H01L27/0629 ,  H01L27/0255 ,  H03K17/063 ,  H03K17/165 ,  H03K17/168 ,  H03K17/567 ,  H03K17/687 ,  H03K2217/0036

摘要： A switching circuit includes: a transistor having a first electrode, a second electrode and a control electrode; a zener diode; and a capacitor. A connection between the first electrode and the second electrode is capable of temporally switching between a condition state and a non-conduction state by switching a control voltage of the transistor. The zener diode and the capacitor are coupled in series between the first electrode and the control electrode of the transistor. The first electrode is a drain or a collector.

摘要翻译： 开关电路包括：具有第一电极，第二电极和控制电极的晶体管; 齐纳二极管; 和电容器。 第一电极和第二电极之间的连接能够通过切换晶体管的控制电压来暂时地在状态和非导通状态之间切换。 齐纳二极管和电容器串联耦合在晶体管的第一电极和控制电极之间。 第一电极是漏极或集电极。

公开(公告)号：US20080230834A1

公开(公告)日：2008-09-25

申请号：US12071411

申请日：2008-02-21

申请人： Nozomu Akagi ,  Shigeki Takahashi ,  Takashi Nakano ,  Yasushi Higuchi ,  Tetsuo Fujii ,  Yoshiyuki Hattori ,  Makoto Kuwahara

发明人： Nozomu Akagi ,  Shigeki Takahashi ,  Takashi Nakano ,  Yasushi Higuchi ,  Tetsuo Fujii ,  Yoshiyuki Hattori ,  Makoto Kuwahara

IPC分类号： H01L27/06

CPC分类号： H01L29/7817 ,  H01L27/0738 ,  H01L29/0696 ,  H01L29/41758 ,  H01L29/42368 ,  H01L29/435 ,  H01L29/4933 ,  H01L29/7824 ,  H01L29/7835

摘要： A semiconductor apparatus comprises: a semiconductor substrate; and a lateral type MIS transistor disposed on a surface part of the semiconductor substrate. The lateral type MIS transistor includes: a line coupled with a gate of the lateral type MIS transistor; a polycrystalline silicon resistor that is provided in the line, and that has a conductivity type opposite to a drain of the lateral type MIS transistor; and an insulating layer through which a drain voltage of the lateral type MIS transistor is applied to the polycrystalline silicon resistor.

摘要翻译： 半导体装置包括：半导体衬底; 以及设置在半导体衬底的表面部分上的横向型MIS晶体管。 横向型MIS晶体管包括：与横向型MIS晶体管的栅极耦合的线; 该多晶硅电阻器设置在该线路中，并且具有与横向型MIS晶体管的漏极相反的导电类型; 以及绝缘层，横向型MIS晶体管的漏极电压通过该绝缘层施加到多晶硅电阻器。

公开(公告)号：US20050133859A1

公开(公告)日：2005-06-23

申请号：US11012116

申请日：2004-12-16

申请人： Makoto Kuwahara ,  Yoshiyuki Hattori ,  Shoichi Yamauchi ,  Mikimasa Suzuki

发明人： Makoto Kuwahara ,  Yoshiyuki Hattori ,  Shoichi Yamauchi ,  Mikimasa Suzuki

IPC分类号： G06F17/50 ,  H01L27/02 ,  H01L29/06 ,  H01L29/76 ,  H01L29/78

CPC分类号： H01L29/7813 ,  G06F17/5068 ,  H01L29/0634

摘要： A semiconductor device is fabricated to include a withstand-voltage assurance layer designed into a multi-dimensional super junction structure and a group of trench gate electrodes, each of which penetrating a body layer in contact with the multi-dimensional super junction structure to reach the multi-dimensional super junction structure, so that dispersions of an on-resistance of the semiconductor device can be reduced. When a position at which the group of trench gate electrodes is created is shifted in one direction, the size of an overlap area common to the group of trench gate electrodes and an n-type column changes. However, the group of trench gate electrodes is oriented in such a way that the changes in overlap-area size are minimized.

摘要翻译： 半导体器件被制造成包括设计成多维超结结构的耐压保证层和一组沟槽栅极电极，每个沟槽栅电极穿透与多维超结结构接触的体层以达到 多维超结结构，能够降低半导体装置的导通电阻的分散。 当形成沟槽栅电极组的位置在一个方向上移动时，沟槽栅电极组和n型列共同的重叠区域的尺寸改变。 然而，沟槽栅电极组被定向成使得重叠区域尺寸的变化最小化。

公开(公告)号：US5388904A

公开(公告)日：1995-02-14

申请号：US185173

申请日：1994-01-24

申请人： Makoto Kuwahara ,  Kakuji Kume ,  Eiichi Masuko ,  Atsushi Saitou ,  Katsuhiro Fukuda ,  Takashi Araki ,  Yuuji Hosoda

发明人： Makoto Kuwahara ,  Kakuji Kume ,  Eiichi Masuko ,  Atsushi Saitou ,  Katsuhiro Fukuda ,  Takashi Araki ,  Yuuji Hosoda

IPC分类号： B29C44/18 ,  F25D23/06 ,  F25D11/00

CPC分类号： F25D23/064 ,  B29C44/18

摘要： A partitioning member having therein a space is provided at the opening of a thermal insulation box having an outer and inner boxes forming a space in between said outer and inner boxes. The two spaces communicate with each other and filled integrally with a thermal insulation material by injecting into the space between said outer and inner box an expandable thermal insulation material, which diffuses into the space inside said partitioning member, to thereby provide in a simple and economical way a thermal insulation box having a small number of components but as uniform thermal insulation.

公开(公告)号：US5174640A

公开(公告)日：1992-12-29

申请号：US648456

申请日：1991-01-30

申请人： Makoto Kuwahara ,  Kakuji Kume ,  Eiichi Masuko ,  Atsushi Saitou ,  Katsuhiro Fukuda ,  Takashi Araki ,  Yuuji Hosoda

发明人： Makoto Kuwahara ,  Kakuji Kume ,  Eiichi Masuko ,  Atsushi Saitou ,  Katsuhiro Fukuda ,  Takashi Araki ,  Yuuji Hosoda

IPC分类号： B29C44/18 ,  F25D23/06

CPC分类号： F25D23/064 ,  B29C44/18

摘要： A partitioning member having therein a space is provided at the opening of a thermal insulation box having an outer and inner boxes forming a space in between said outer and inner boxes. The two spaces communicate with each other and filled integrally with a thermal insulation material by injecting into the space between said outer and inner box an expandable thermal insulation material, which diffuses into the space inside said partitioning member, to thereby provide in a simple and economical way a thermal insulation box having a small number of components but as uniform thermal insulation.

摘要翻译： 具有空间的分隔构件设置在隔热箱的开口处，该隔热箱具有形成在所述外箱和内箱之间的空间的外箱和内箱。 这两个空间彼此连通并且通过将隔热材料注入到所述外箱和内箱之间的空间内与隔热材料一体地填充，所述可膨胀隔热材料扩散到所述分隔件内部的空间中，从而提供简单且经济的 方式是具有少量部件但是均匀隔热的保温箱。